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yuhei1horibe/Example3.v

Last active April 29, 2019 01:33
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Example3.v
// Add user logic here
wire [4:0]out_from_adder;
// Assign result
always @( posedge S_AXI_ACLK)
begin
if (S_AXI_ARESETN == 1'b0 )
begin
output_reg <= 32'h00000000;
end
else
begin
output_reg <= {27'h0, out_from_adder[4:0]};
end
end
// Wire adder
adder4 ADDER_1(
.a (input_a_reg[3:0]),
.b (input_b_reg[3:0]),
.y (out_from_adder[4:0]));
assign LED_OUT[7:0] = { 3'h0, out_from_adder[4:0] };
// User logic ends
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