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| always @( posedge S_AXI_ACLK ) | |
| begin | |
| if ( S_AXI_ARESETN == 1'b0 ) | |
| begin | |
| input_a_reg <= 0; | |
| input_b_reg <= 0; | |
| //output_reg <= 0; | |
| spare_reg <= 0; | |
| end | |
| else begin | |
| if (slv_reg_wren) | |
| begin | |
| case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] ) | |
| 2'h0: | |
| for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) | |
| if ( S_AXI_WSTRB[byte_index] == 1 ) begin | |
| // Respective byte enables are asserted as per write strobes | |
| // Slave register 0 | |
| input_a_reg[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; | |
| end | |
| 2'h1: | |
| for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) | |
| if ( S_AXI_WSTRB[byte_index] == 1 ) begin | |
| // Respective byte enables are asserted as per write strobes | |
| // Slave register 1 | |
| input_b_reg[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; | |
| end | |
| //2'h2: | |
| // for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) | |
| // if ( S_AXI_WSTRB[byte_index] == 1 ) begin | |
| // // Respective byte enables are asserted as per write strobes | |
| // // Slave register 2 | |
| // output_reg[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; | |
| // end | |
| 2'h3: | |
| for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) | |
| if ( S_AXI_WSTRB[byte_index] == 1 ) begin | |
| // Respective byte enables are asserted as per write strobes | |
| // Slave register 3 | |
| spare_reg[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; | |
| end | |
| default : begin | |
| input_a_reg <= input_a_reg; | |
| input_b_reg <= input_b_reg; | |
| //output_reg <= output_reg; | |
| spare_reg <= spare_reg; | |
| end | |
| endcase | |
| end | |
| end | |
| end |
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