Skip to content

Instantly share code, notes, and snippets.

@ivg

ivg/decode_it.ml

Created November 17, 2021 21:55
Show Gist options

  • Select an option

    Learn more about clone URLs
  • Save ivg/4b07e247f65a9c2ce38f527c66675864 to your computer and use it in GitHub Desktop.

Select an option

Learn more about clone URLs
Save ivg/4b07e247f65a9c2ce38f527c66675864 to your computer and use it in GitHub Desktop.
Download ZIP

Revisions

  1. ivg created this gist Nov 17, 2021.
    50 changes: 50 additions & 0 deletions decode_it.ml
    View file
    Original file line number Diff line number Diff line change
    @@ -0,0 +1,50 @@
    let of_int_exn = function
    | 0 -> `EQ
    | 1 -> `NE
    | 2 -> `CS
    | 3 -> `CC
    | 4 -> `MI
    | 5 -> `PL
    | 6 -> `VS
    | 7 -> `VC
    | 8 -> `HI
    | 9 -> `LS
    | 10 -> `GE
    | 11 -> `LT
    | 12 -> `GT
    | 13 -> `LE
    | 14 -> `AL
    | _ -> invalid_arg "not a condition"

    (**
    llvm represents [itxyz], as
    - [xyz1] ; 4 instructions
    - [xy10] ; 3 instructions
    - [x100] ; 2 instructions
    - [1000] ; 1 instruction,
    where [x],[y],[z] bits are set to [1] if the
    cond has to be negated, i.e., [t] is [0],
    and [e] is [1].
    Examples,
    {v
    it => 1000
    itt => 0100
    itete => 1011.
    v}
    The condition codes in ARM are made so that the
    flipping the least significant bit is the same
    as negating it, so we can xor the least significant
    bit of the condition with with most significant
    bit of the mask. *)
    let decode_llvm_it ~cond ~mask =
    let rec gen conds = function
    | 0b1000 -> List.rev conds
    | mask ->
    let flip = mask lsr 3 in
    let mask = mask lsl 1 land 0b1111 in
    gen (of_int_exn (cond lxor flip) :: conds) mask in
    gen [of_int_exn cond] mask