gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/APU
| Metric | Before | After | Delta |
|---|---|---|---|
| antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold | -0.2942 | -0.2942 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup | 0.2920 | 0.2920 | 0.0000 (0.0000%) ⭕ |
| design__core__area | 285113 | 285113 | 0 (0.0000%) ⭕ |
| design__die__area | 310525 | 310525 | 0 (0.0000%) ⭕ |
| design__instance__area | 285113 | 285113 | 0 (0.0000%) ⭕ |
| design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count | 4 | 4 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count | 209 | 209 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count | 2328 | 2328 | 0 (0.0000%) ⭕ |
| ir__drop__avg | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
| ir__drop__worst | 0.0004 | 0.0004 | 0.0000 (0.0000%) ⭕ |
| ir__voltage__worst | 5 | 5 | 0 (0.0000%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| power__internal__total | 0.0065 | 0.0065 | 0.0000 (0.0000%) ⭕ |
| power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
| power__switching__total | 0.0034 | 0.0034 | 0.0000 (0.0000%) ⭕ |
| power__total | 0.0099 | 0.0099 | 0.0000 (0.0000%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_ff_n40C_5v50 | -0.3032 | -0.3032 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_ff_n40C_5v50 | 0.2999 | 0.2999 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ff_n40C_5v50 | 3 | 3 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ff_n40C_5v50 | 209 | 209 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ff_n40C_5v50 | 44 | 44 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_ss_125C_4v50 | -0.3995 | -0.3995 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_ss_125C_4v50 | 0.3851 | 0.3851 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ss_125C_4v50 | 4 | 4 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ss_125C_4v50 | 209 | 209 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ss_125C_4v50 | 2328 | 2328 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_tt_025C_5v00 | -0.3334 | -0.3334 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_tt_025C_5v00 | 0.3266 | 0.3266 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_tt_025C_5v00 | 3 | 3 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_tt_025C_5v00 | 209 | 209 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_tt_025C_5v00 | 66 | 66 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_ff_n40C_5v50 | -0.2942 | -0.2942 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_ff_n40C_5v50 | 0.2920 | 0.2920 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ff_n40C_5v50 | 2 | 2 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ff_n40C_5v50 | 209 | 209 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_ss_125C_4v50 | -0.3760 | -0.3760 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_ss_125C_4v50 | 0.3664 | 0.3664 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ss_125C_4v50 | 3 | 3 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ss_125C_4v50 | 209 | 209 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ss_125C_4v50 | 1327 | 1327 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_tt_025C_5v00 | -0.3197 | -0.3197 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_tt_025C_5v00 | 0.3152 | 0.3152 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_tt_025C_5v00 | 2 | 2 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_tt_025C_5v00 | 209 | 209 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_tt_025C_5v00 | 66 | 66 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_ff_n40C_5v50 | -0.2983 | -0.2983 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_ff_n40C_5v50 | 0.2957 | 0.2957 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ff_n40C_5v50 | 3 | 3 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ff_n40C_5v50 | 209 | 209 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_ss_125C_4v50 | -0.3869 | -0.3869 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_ss_125C_4v50 | 0.3753 | 0.3753 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ss_125C_4v50 | 3 | 3 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ss_125C_4v50 | 209 | 209 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ss_125C_4v50 | 1801 | 1801 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_tt_025C_5v00 | -0.3260 | -0.3260 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_tt_025C_5v00 | 0.3205 | 0.3205 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_tt_025C_5v00 | 3 | 3 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_tt_025C_5v00 | 209 | 209 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_tt_025C_5v00 | 66 | 66 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/blink
| Metric | Before | After | Delta |
|---|---|---|---|
| timing__setup__tns | 0.0000 | -0.1444 | -0.1444 |
| timing__setup__wns | 0.0000 | -0.1444 | -0.1444 |
| timing__setup_r2r_vio__count | 0 | 2 | 2 |
| timing__setup_vio__count | 0 | 2 | 2 |
| timing__setup__tns__corner:max_ss_125C_4v50 | 0.0000 | -0.1444 | -0.1444 |
| timing__setup__wns__corner:max_ss_125C_4v50 | 0.0000 | -0.1444 | -0.1444 |
| timing__setup_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 1 | 1 |
| timing__setup_vio__count__corner:max_ss_125C_4v50 | 0 | 1 | 1 |
| timing__setup__tns__corner:nom_ss_125C_4v50 | 0.0000 | -0.0650 | -0.0650 |
| timing__setup__wns__corner:nom_ss_125C_4v50 | 0.0000 | -0.0650 | -0.0650 |
| timing__setup_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 1 | 1 |
| timing__setup_vio__count__corner:nom_ss_125C_4v50 | 0 | 1 | 1 |
| ir__drop__avg | 0.0003 | 0.0004 | 0.0000 (+9.7345%) ❗ |
| ir__drop__worst | 0.0008 | 0.0009 | 0.0001 (+19.1546%) ❗ |
| power__internal__total | 0.0038 | 0.0038 | 0.0000 (+0.0113%) ❗ |
| clock__skew__worst_hold__corner:max_ss_125C_4v50 | -0.2556 | -0.2553 | 0.0004 (-0.1388%) ❗ |
| clock__skew__worst_setup__corner:max_ss_125C_4v50 | 0.2556 | 0.2554 | -0.0002 (-0.0877%) ❗ |
| clock__skew__worst_hold__corner:min_ss_125C_4v50 | -0.2545 | -0.2539 | 0.0005 (-0.2100%) ❗ |
| clock__skew__worst_setup__corner:min_ss_125C_4v50 | 0.2545 | 0.2541 | -0.0004 (-0.1657%) ❗ |
| clock__skew__worst_hold__corner:min_tt_025C_5v00 | -0.2524 | -0.2523 | 0.0001 (-0.0455%) ❗ |
| clock__skew__worst_setup__corner:min_tt_025C_5v00 | 0.2524 | 0.2524 | -0.0000 (-0.0011%) ❗ |
| clock__skew__worst_hold__corner:nom_ss_125C_4v50 | -0.2550 | -0.2546 | 0.0005 (-0.1781%) ❗ |
| clock__skew__worst_setup__corner:nom_ss_125C_4v50 | 0.2550 | 0.2547 | -0.0003 (-0.1296%) ❗ |
| clock__skew__worst_hold__corner:nom_tt_025C_5v00 | -0.2527 | -0.2527 | 0.0001 (-0.0203%) ❗ |
| clock__skew__worst_hold | -0.2515 | -0.2517 | -0.0002 (+0.0964%) ⭕ |
| clock__skew__worst_setup | 0.2515 | 0.2517 | 0.0003 (+0.1004%) ⭕ |
| design__core__area | 6960.9800 | 6146.5600 | -814.4200 (-11.6998%) ⭕ |
| design__die__area | 11390.1000 | 10176.3000 | -1213.8000 (-10.6566%) ⭕ |
| design__instance__area | 6960.9800 | 6146.5600 | -814.4200 (-11.6998%) ⭕ |
| power__leakage__total | 0.0000 | 0.0000 | -0.0000 (-11.9156%) ⭕ |
| power__switching__total | 0.0007 | 0.0007 | -0.0000 (-4.2396%) ⭕ |
| power__total | 0.0045 | 0.0045 | -0.0000 (-0.6606%) ⭕ |
| clock__skew__worst_hold__corner:max_ff_n40C_5v50 | -0.2519 | -0.2521 | -0.0002 (+0.0798%) ⭕ |
| clock__skew__worst_setup__corner:max_ff_n40C_5v50 | 0.2519 | 0.2522 | 0.0003 (+0.1307%) ⭕ |
| clock__skew__worst_hold__corner:max_tt_025C_5v00 | -0.2530 | -0.2531 | -0.0000 (+0.0099%) ⭕ |
| clock__skew__worst_setup__corner:max_tt_025C_5v00 | 0.2530 | 0.2532 | 0.0002 (+0.0612%) ⭕ |
| clock__skew__worst_hold__corner:min_ff_n40C_5v50 | -0.2515 | -0.2517 | -0.0002 (+0.0964%) ⭕ |
| clock__skew__worst_setup__corner:min_ff_n40C_5v50 | 0.2515 | 0.2517 | 0.0003 (+0.1004%) ⭕ |
| clock__skew__worst_hold__corner:nom_ff_n40C_5v50 | -0.2517 | -0.2519 | -0.0002 (+0.0897%) ⭕ |
| clock__skew__worst_setup__corner:nom_ff_n40C_5v50 | 0.2517 | 0.2519 | 0.0003 (+0.1018%) ⭕ |
| clock__skew__worst_setup__corner:nom_tt_025C_5v00 | 0.2527 | 0.2528 | 0.0001 (+0.0284%) ⭕ |
| antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| ir__voltage__worst | 5 | 5 | 0 (0.0000%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/cell_inverter
| Metric | Before | After | Delta |
|---|---|---|---|
| design__instance__area | 8.7808 | 8.7808 | 0.0000 (0.0000%) ⭕ |
| design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/hold_violations_1
| Metric | Before | After | Delta |
|---|---|---|---|
| antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold | -0.2513 | -0.2513 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup | 0.2513 | 0.2513 | 0.0000 (0.0000%) ⭕ |
| design__core__area | 6776.5800 | 6776.5800 | 0.0000 (0.0000%) ⭕ |
| design__die__area | 10903.8000 | 10903.8000 | 0.0000 (0.0000%) ⭕ |
| design__instance__area | 6776.5800 | 6776.5800 | 0.0000 (0.0000%) ⭕ |
| design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| ir__drop__avg | 0.0003 | 0.0003 | 0.0000 (0.0000%) ⭕ |
| ir__drop__worst | 0.0007 | 0.0007 | 0.0000 (0.0000%) ⭕ |
| ir__voltage__worst | 5 | 5 | 0 (0.0000%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| power__internal__total | 0.0042 | 0.0042 | 0.0000 (0.0000%) ⭕ |
| power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
| power__switching__total | 0.0008 | 0.0008 | 0.0000 (0.0000%) ⭕ |
| power__total | 0.0050 | 0.0050 | 0.0000 (0.0000%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_ff_n40C_5v50 | -0.2515 | -0.2515 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_ff_n40C_5v50 | 0.2515 | 0.2515 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_ss_125C_4v50 | -0.2539 | -0.2539 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_ss_125C_4v50 | 0.2539 | 0.2539 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_tt_025C_5v00 | -0.2523 | -0.2523 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_tt_025C_5v00 | 0.2522 | 0.2522 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_ff_n40C_5v50 | -0.2513 | -0.2513 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_ff_n40C_5v50 | 0.2513 | 0.2513 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_ss_125C_4v50 | -0.2533 | -0.2533 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_ss_125C_4v50 | 0.2532 | 0.2532 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_tt_025C_5v00 | -0.2519 | -0.2519 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_tt_025C_5v00 | 0.2519 | 0.2519 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_ff_n40C_5v50 | -0.2514 | -0.2514 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_ff_n40C_5v50 | 0.2514 | 0.2514 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_ss_125C_4v50 | -0.2535 | -0.2535 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_ss_125C_4v50 | 0.2535 | 0.2535 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_tt_025C_5v00 | -0.2521 | -0.2521 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_tt_025C_5v00 | 0.2520 | 0.2520 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/hold_violations_2
| Metric | Before | After | Delta |
|---|---|---|---|
| antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold | -0.2515 | -0.2515 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup | 0.2516 | 0.2516 | 0.0000 (0.0000%) ⭕ |
| design__core__area | 6776.5800 | 6776.5800 | 0.0000 (0.0000%) ⭕ |
| design__die__area | 10903.8000 | 10903.8000 | 0.0000 (0.0000%) ⭕ |
| design__instance__area | 6776.5800 | 6776.5800 | 0.0000 (0.0000%) ⭕ |
| design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| ir__drop__avg | 0.0003 | 0.0003 | 0.0000 (0.0000%) ⭕ |
| ir__drop__worst | 0.0007 | 0.0007 | 0.0000 (0.0000%) ⭕ |
| ir__voltage__worst | 5 | 5 | 0 (0.0000%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| power__internal__total | 0.0042 | 0.0042 | 0.0000 (0.0000%) ⭕ |
| power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
| power__switching__total | 0.0008 | 0.0008 | 0.0000 (0.0000%) ⭕ |
| power__total | 0.0050 | 0.0050 | 0.0000 (0.0000%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns | -1.4170 | -1.4170 | 0.0000 (0.0000%) ⭕ |
| timing__hold__wns | -1.4170 | -1.4170 | 0.0000 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count | 9 | 9 | 0 (0.0000%) ⭕ |
| timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_ff_n40C_5v50 | -0.2518 | -0.2518 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_ff_n40C_5v50 | 0.2519 | 0.2519 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ff_n40C_5v50 | -0.6842 | -0.6842 | 0.0000 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ff_n40C_5v50 | -0.6842 | -0.6842 | 0.0000 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_ss_125C_4v50 | -0.2544 | -0.2544 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_ss_125C_4v50 | 0.2545 | 0.2545 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ss_125C_4v50 | -1.4170 | -1.4170 | 0.0000 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ss_125C_4v50 | -1.4170 | -1.4170 | 0.0000 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_tt_025C_5v00 | -0.2526 | -0.2526 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_tt_025C_5v00 | 0.2527 | 0.2527 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_tt_025C_5v00 | -0.9103 | -0.9103 | 0.0000 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_tt_025C_5v00 | -0.9103 | -0.9103 | 0.0000 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_ff_n40C_5v50 | -0.2515 | -0.2515 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_ff_n40C_5v50 | 0.2516 | 0.2516 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ff_n40C_5v50 | -0.6832 | -0.6832 | 0.0000 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ff_n40C_5v50 | -0.6832 | -0.6832 | 0.0000 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_ss_125C_4v50 | -0.2537 | -0.2537 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_ss_125C_4v50 | 0.2537 | 0.2537 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ss_125C_4v50 | -1.4139 | -1.4139 | 0.0000 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ss_125C_4v50 | -1.4139 | -1.4139 | 0.0000 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_tt_025C_5v00 | -0.2522 | -0.2522 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_tt_025C_5v00 | 0.2523 | 0.2523 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_tt_025C_5v00 | -0.9088 | -0.9088 | 0.0000 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_tt_025C_5v00 | -0.9088 | -0.9088 | 0.0000 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_ff_n40C_5v50 | -0.2517 | -0.2517 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_ff_n40C_5v50 | 0.2517 | 0.2517 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ff_n40C_5v50 | -0.6836 | -0.6836 | 0.0000 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ff_n40C_5v50 | -0.6836 | -0.6836 | 0.0000 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_ss_125C_4v50 | -0.2540 | -0.2540 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_ss_125C_4v50 | 0.2541 | 0.2541 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ss_125C_4v50 | -1.4153 | -1.4153 | 0.0000 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ss_125C_4v50 | -1.4153 | -1.4153 | 0.0000 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_tt_025C_5v00 | -0.2524 | -0.2524 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_tt_025C_5v00 | 0.2525 | 0.2525 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_tt_025C_5v00 | -0.9095 | -0.9095 | 0.0000 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_tt_025C_5v00 | -0.9095 | -0.9095 | 0.0000 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/hold_violations_3
| Metric | Before | After | Delta |
|---|---|---|---|
| antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold | -0.2511 | -0.2511 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup | 0.2512 | 0.2512 | 0.0000 (0.0000%) ⭕ |
| design__core__area | 15344.4000 | 15344.4000 | 0.0000 (0.0000%) ⭕ |
| design__die__area | 18225 | 18225 | 0 (0.0000%) ⭕ |
| design__instance__area | 13435.5000 | 13435.5000 | 0.0000 (0.0000%) ⭕ |
| design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| ir__drop__avg | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
| ir__drop__worst | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
| ir__voltage__worst | 5 | 5 | 0 (0.0000%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| power__internal__total | 0.0016 | 0.0016 | 0.0000 (0.0000%) ⭕ |
| power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
| power__switching__total | 0.0003 | 0.0003 | 0.0000 (0.0000%) ⭕ |
| power__total | 0.0018 | 0.0018 | 0.0000 (0.0000%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_ff_n40C_5v50 | -0.2514 | -0.2514 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_ff_n40C_5v50 | 0.2515 | 0.2515 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_ss_125C_4v50 | -0.2527 | -0.2527 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_ss_125C_4v50 | 0.2528 | 0.2528 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_tt_025C_5v00 | -0.2518 | -0.2518 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_tt_025C_5v00 | 0.2519 | 0.2519 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_ff_n40C_5v50 | -0.2511 | -0.2511 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_ff_n40C_5v50 | 0.2512 | 0.2512 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_ss_125C_4v50 | -0.2521 | -0.2521 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_ss_125C_4v50 | 0.2522 | 0.2522 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_tt_025C_5v00 | -0.2514 | -0.2514 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_tt_025C_5v00 | 0.2515 | 0.2515 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_ff_n40C_5v50 | -0.2512 | -0.2512 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_ff_n40C_5v50 | 0.2513 | 0.2513 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_ss_125C_4v50 | -0.2524 | -0.2524 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_ss_125C_4v50 | 0.2525 | 0.2525 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_tt_025C_5v00 | -0.2516 | -0.2516 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_tt_025C_5v00 | 0.2517 | 0.2517 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/inverter
| Metric | Before | After | Delta |
|---|---|---|---|
| antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
| design__core__area | 570.7520 | 570.7520 | 0.0000 (0.0000%) ⭕ |
| design__die__area | 2500 | 2500 | 0 (0.0000%) ⭕ |
| design__instance__area | 570.7520 | 570.7520 | 0.0000 (0.0000%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/latch_bad
| Metric | Before | After | Delta |
|---|---|---|---|
| design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/latch_good
| Metric | Before | After | Delta |
|---|---|---|---|
| design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/spm
| Metric | Before | After | Delta |
|---|---|---|---|
| antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold | -0.2535 | -0.2535 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup | 0.2539 | 0.2539 | 0.0000 (0.0000%) ⭕ |
| design__core__area | 21280.3000 | 21280.3000 | 0.0000 (0.0000%) ⭕ |
| design__die__area | 28670.3000 | 28670.3000 | 0.0000 (0.0000%) ⭕ |
| design__instance__area | 20792.9000 | 20792.9000 | 0.0000 (0.0000%) ⭕ |
| design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| ir__drop__avg | 0.0006 | 0.0006 | 0.0000 (0.0000%) ⭕ |
| ir__drop__worst | 0.0012 | 0.0012 | 0.0000 (0.0000%) ⭕ |
| ir__voltage__worst | 5 | 5 | 0 (0.0000%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| power__internal__total | 0.0131 | 0.0131 | 0.0000 (0.0000%) ⭕ |
| power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
| power__switching__total | 0.0033 | 0.0033 | 0.0000 (0.0000%) ⭕ |
| power__total | 0.0163 | 0.0163 | 0.0000 (0.0000%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_ff_n40C_5v50 | -0.2545 | -0.2545 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_ff_n40C_5v50 | 0.2552 | 0.2552 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_ss_125C_4v50 | -0.2636 | -0.2636 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_ss_125C_4v50 | 0.2624 | 0.2624 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_tt_025C_5v00 | -0.2568 | -0.2568 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_tt_025C_5v00 | 0.2573 | 0.2573 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_ff_n40C_5v50 | -0.2535 | -0.2535 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_ff_n40C_5v50 | 0.2539 | 0.2539 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_ss_125C_4v50 | -0.2606 | -0.2606 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_ss_125C_4v50 | 0.2592 | 0.2592 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_tt_025C_5v00 | -0.2553 | -0.2553 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_tt_025C_5v00 | 0.2555 | 0.2555 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_ff_n40C_5v50 | -0.2540 | -0.2540 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_ff_n40C_5v50 | 0.2545 | 0.2545 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_ss_125C_4v50 | -0.2619 | -0.2619 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_ss_125C_4v50 | 0.2607 | 0.2607 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_tt_025C_5v00 | -0.2559 | -0.2559 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_tt_025C_5v00 | 0.2563 | 0.2563 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/usb
| Metric | Before | After | Delta |
|---|---|---|---|
| antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold | -0.2591 | -0.2591 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup | 0.2575 | 0.2575 | 0.0000 (0.0000%) ⭕ |
| design__core__area | 59885.1000 | 59885.1000 | 0.0000 (0.0000%) ⭕ |
| design__die__area | 72318.4000 | 72318.4000 | 0.0000 (0.0000%) ⭕ |
| design__instance__area | 59885.1000 | 59885.1000 | 0.0000 (0.0000%) ⭕ |
| design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count | 75 | 75 | 0 (0.0000%) ⭕ |
| ir__drop__avg | 0.0004 | 0.0004 | 0.0000 (0.0000%) ⭕ |
| ir__drop__worst | 0.0010 | 0.0010 | 0.0000 (0.0000%) ⭕ |
| ir__voltage__worst | 5 | 5 | 0 (0.0000%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| power__internal__total | 0.0251 | 0.0251 | 0.0000 (0.0000%) ⭕ |
| power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
| power__switching__total | 0.0070 | 0.0070 | 0.0000 (0.0000%) ⭕ |
| power__total | 0.0321 | 0.0321 | 0.0000 (0.0000%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns | -20.6021 | -20.6021 | 0.0000 (0.0000%) ⭕ |
| timing__setup__wns | -1.4084 | -1.4084 | 0.0000 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count | 43 | 43 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count | 111 | 111 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_ff_n40C_5v50 | -0.2609 | -0.2609 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_ff_n40C_5v50 | 0.2600 | 0.2600 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_ss_125C_4v50 | -0.2763 | -0.2763 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_ss_125C_4v50 | 0.2762 | 0.2762 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ss_125C_4v50 | 75 | 75 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ss_125C_4v50 | -20.6021 | -20.6021 | 0.0000 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ss_125C_4v50 | -1.4084 | -1.4084 | 0.0000 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ss_125C_4v50 | 23 | 23 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ss_125C_4v50 | 58 | 58 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_tt_025C_5v00 | -0.2655 | -0.2655 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_tt_025C_5v00 | 0.2649 | 0.2649 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_ff_n40C_5v50 | -0.2591 | -0.2591 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_ff_n40C_5v50 | 0.2575 | 0.2575 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_ss_125C_4v50 | -0.2715 | -0.2715 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_ss_125C_4v50 | 0.2707 | 0.2707 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ss_125C_4v50 | 26 | 26 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ss_125C_4v50 | -4.3043 | -4.3043 | 0.0000 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ss_125C_4v50 | -0.8100 | -0.8100 | 0.0000 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ss_125C_4v50 | 6 | 6 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ss_125C_4v50 | 17 | 17 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_tt_025C_5v00 | -0.2629 | -0.2629 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_tt_025C_5v00 | 0.2615 | 0.2615 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_ff_n40C_5v50 | -0.2600 | -0.2600 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_ff_n40C_5v50 | 0.2587 | 0.2587 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_ss_125C_4v50 | -0.2735 | -0.2735 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_ss_125C_4v50 | 0.2730 | 0.2730 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ss_125C_4v50 | 48 | 48 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ss_125C_4v50 | -8.7683 | -8.7683 | 0.0000 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ss_125C_4v50 | -1.0834 | -1.0834 | 0.0000 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ss_125C_4v50 | 14 | 14 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ss_125C_4v50 | 36 | 36 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_tt_025C_5v00 | -0.2641 | -0.2641 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_tt_025C_5v00 | 0.2629 | 0.2629 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/usb_cdc_core
| Metric | Before | After | Delta |
|---|---|---|---|
| antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold | -0.2853 | -0.2853 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup | 0.2852 | 0.2852 | 0.0000 (0.0000%) ⭕ |
| design__core__area | 158083 | 158083 | 0 (0.0000%) ⭕ |
| design__die__area | 177793 | 177793 | 0 (0.0000%) ⭕ |
| design__instance__area | 158083 | 158083 | 0 (0.0000%) ⭕ |
| design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count | 103 | 103 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count | 384 | 384 | 0 (0.0000%) ⭕ |
| ir__drop__avg | 0.0003 | 0.0003 | 0.0000 (0.0000%) ⭕ |
| ir__drop__worst | 0.0018 | 0.0018 | 0.0000 (0.0000%) ⭕ |
| ir__voltage__worst | 5 | 5 | 0 (0.0000%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| power__internal__total | 0.0426 | 0.0426 | 0.0000 (0.0000%) ⭕ |
| power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
| power__switching__total | 0.0197 | 0.0197 | 0.0000 (0.0000%) ⭕ |
| power__total | 0.0623 | 0.0623 | 0.0000 (0.0000%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns | -508.3252 | -508.3252 | 0.0000 (0.0000%) ⭕ |
| timing__setup__wns | -3.4660 | -3.4660 | 0.0000 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count | 476 | 476 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count | 968 | 968 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_ff_n40C_5v50 | -0.2899 | -0.2899 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_ff_n40C_5v50 | 0.2918 | 0.2918 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ff_n40C_5v50 | 103 | 103 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_ss_125C_4v50 | -0.3621 | -0.3621 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_ss_125C_4v50 | 0.3671 | 0.3671 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ss_125C_4v50 | 103 | 103 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ss_125C_4v50 | 384 | 384 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ss_125C_4v50 | -508.3252 | -508.3252 | 0.0000 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ss_125C_4v50 | -3.4660 | -3.4660 | 0.0000 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ss_125C_4v50 | 169 | 169 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ss_125C_4v50 | 345 | 345 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_tt_025C_5v00 | -0.3124 | -0.3124 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_tt_025C_5v00 | 0.3154 | 0.3154 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_tt_025C_5v00 | 103 | 103 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_ff_n40C_5v50 | -0.2853 | -0.2853 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_ff_n40C_5v50 | 0.2852 | 0.2852 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ff_n40C_5v50 | 103 | 103 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_ss_125C_4v50 | -0.3502 | -0.3502 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_ss_125C_4v50 | 0.3500 | 0.3500 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ss_125C_4v50 | 103 | 103 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ss_125C_4v50 | 186 | 186 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ss_125C_4v50 | -333.0201 | -333.0201 | 0.0000 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ss_125C_4v50 | -2.6433 | -2.6433 | 0.0000 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ss_125C_4v50 | 150 | 150 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ss_125C_4v50 | 302 | 302 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_tt_025C_5v00 | -0.3055 | -0.3055 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_tt_025C_5v00 | 0.3054 | 0.3054 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_tt_025C_5v00 | 103 | 103 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_ff_n40C_5v50 | -0.2874 | -0.2874 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_ff_n40C_5v50 | 0.2883 | 0.2883 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ff_n40C_5v50 | 103 | 103 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_ss_125C_4v50 | -0.3555 | -0.3555 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_ss_125C_4v50 | 0.3574 | 0.3574 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ss_125C_4v50 | 103 | 103 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ss_125C_4v50 | 263 | 263 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ss_125C_4v50 | -409.6397 | -409.6397 | 0.0000 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ss_125C_4v50 | -3.0184 | -3.0184 | 0.0000 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ss_125C_4v50 | 157 | 157 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ss_125C_4v50 | 321 | 321 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_tt_025C_5v00 | -0.3086 | -0.3086 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_tt_025C_5v00 | 0.3096 | 0.3096 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_tt_025C_5v00 | 103 | 103 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/wbqspiflash
| Metric | Before | After | Delta |
|---|---|---|---|
| timing__setup__tns | -387.9658 | -334.6869 | 53.2789 (-13.7329%) |
| timing__setup__wns | -3.6852 | -3.5548 | 0.1303 (-3.5363%) |
| timing__setup_r2r_vio__count | 607 | 542 | -65 (-10.7084%) |
| timing__setup_vio__count | 619 | 553 | -66 (-10.6624%) |
| timing__setup__tns__corner:max_ss_125C_4v50 | -387.9658 | -334.6869 | 53.2789 (-13.7329%) |
| timing__setup__wns__corner:max_ss_125C_4v50 | -3.6852 | -3.5548 | 0.1303 (-3.5363%) |
| timing__setup_r2r_vio__count__corner:max_ss_125C_4v50 | 204 | 182 | -22 (-10.7843%) |
| timing__setup_vio__count__corner:max_ss_125C_4v50 | 208 | 186 | -22 (-10.5769%) |
| timing__setup__tns__corner:min_ss_125C_4v50 | -271.1681 | -235.5969 | 35.5712 (-13.1178%) |
| timing__setup__wns__corner:min_ss_125C_4v50 | -3.0247 | -2.8131 | 0.2117 (-6.9978%) |
| timing__setup_r2r_vio__count__corner:min_ss_125C_4v50 | 200 | 179 | -21 (-10.5000%) |
| timing__setup_vio__count__corner:min_ss_125C_4v50 | 204 | 182 | -22 (-10.7843%) |
| timing__setup__tns__corner:nom_ss_125C_4v50 | -323.4310 | -279.5917 | 43.8393 (-13.5544%) |
| timing__setup__wns__corner:nom_ss_125C_4v50 | -3.3247 | -3.1460 | 0.1787 (-5.3744%) |
| timing__setup_r2r_vio__count__corner:nom_ss_125C_4v50 | 203 | 181 | -22 (-10.8374%) |
| timing__setup_vio__count__corner:nom_ss_125C_4v50 | 207 | 185 | -22 (-10.6280%) |
| ir__drop__avg | 0.0019 | 0.0020 | 0.0001 (+4.7368%) ❗ |
| power__internal__total | 0.0923 | 0.0930 | 0.0007 (+0.7550%) ❗ |
| design__max_cap_violation__count__corner:min_ff_n40C_5v50 | 0 | 1 | 1 ❗ |
| design__max_cap_violation__count__corner:min_ss_125C_4v50 | 0 | 1 | 1 ❗ |
| design__max_slew_violation__count__corner:min_ss_125C_4v50 | 29 | 30 | 1 (+3.4483%) ❗ |
| design__max_cap_violation__count__corner:min_tt_025C_5v00 | 0 | 1 | 1 ❗ |
| design__max_cap_violation__count__corner:nom_ff_n40C_5v50 | 0 | 1 | 1 ❗ |
| design__max_cap_violation__count__corner:nom_ss_125C_4v50 | 0 | 1 | 1 ❗ |
| design__max_cap_violation__count__corner:nom_tt_025C_5v00 | 0 | 1 | 1 ❗ |
| clock__skew__worst_hold | -0.2767 | -0.2921 | -0.0154 (+5.5645%) ⭕ |
| clock__skew__worst_setup | 0.2779 | 0.2930 | 0.0151 (+5.4321%) ⭕ |
| design__core__area | 99223.0000 | 94345.3000 | -4877.7000 (-4.9159%) ⭕ |
| design__die__area | 115082 | 109785 | -5297 (-4.6028%) ⭕ |
| design__instance__area | 99223.0000 | 94345.3000 | -4877.7000 (-4.9159%) ⭕ |
| design__max_cap_violation__count | 2 | 1 | -1 (-50.0000%) ⭕ |
| design__max_slew_violation__count | 104 | 71 | -33 (-31.7308%) ⭕ |
| ir__drop__worst | 0.0075 | 0.0068 | -0.0007 (-9.1755%) ⭕ |
| power__leakage__total | 0.0000 | 0.0000 | -0.0000 (-2.0748%) ⭕ |
| power__switching__total | 0.0647 | 0.0634 | -0.0012 (-1.9309%) ⭕ |
| power__total | 0.1570 | 0.1564 | -0.0006 (-0.3513%) ⭕ |
| clock__skew__worst_hold__corner:max_ff_n40C_5v50 | -0.2861 | -0.3058 | -0.0197 (+6.8828%) ⭕ |
| clock__skew__worst_setup__corner:max_ff_n40C_5v50 | 0.2879 | 0.3068 | 0.0189 (+6.5700%) ⭕ |
| clock__skew__worst_hold__corner:max_ss_125C_4v50 | -0.3490 | -0.3950 | -0.0460 (+13.1712%) ⭕ |
| clock__skew__worst_setup__corner:max_ss_125C_4v50 | 0.3489 | 0.4009 | 0.0520 (+14.9123%) ⭕ |
| design__max_cap_violation__count__corner:max_ss_125C_4v50 | 2 | 1 | -1 (-50.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ss_125C_4v50 | 104 | 71 | -33 (-31.7308%) ⭕ |
| clock__skew__worst_hold__corner:max_tt_025C_5v00 | -0.3060 | -0.3339 | -0.0279 (+9.1287%) ⭕ |
| clock__skew__worst_setup__corner:max_tt_025C_5v00 | 0.3065 | 0.3365 | 0.0300 (+9.8046%) ⭕ |
| design__max_cap_violation__count__corner:max_tt_025C_5v00 | 2 | 1 | -1 (-50.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_ff_n40C_5v50 | -0.2767 | -0.2921 | -0.0154 (+5.5645%) ⭕ |
| clock__skew__worst_setup__corner:min_ff_n40C_5v50 | 0.2779 | 0.2930 | 0.0151 (+5.4321%) ⭕ |
| clock__skew__worst_hold__corner:min_ss_125C_4v50 | -0.3234 | -0.3595 | -0.0360 (+11.1391%) ⭕ |
| clock__skew__worst_setup__corner:min_ss_125C_4v50 | 0.3234 | 0.3641 | 0.0407 (+12.5985%) ⭕ |
| clock__skew__worst_hold__corner:min_tt_025C_5v00 | -0.2915 | -0.3134 | -0.0219 (+7.5133%) ⭕ |
| clock__skew__worst_setup__corner:min_tt_025C_5v00 | 0.2916 | 0.3154 | 0.0238 (+8.1536%) ⭕ |
| clock__skew__worst_hold__corner:nom_ff_n40C_5v50 | -0.2810 | -0.2983 | -0.0173 (+6.1656%) ⭕ |
| clock__skew__worst_setup__corner:nom_ff_n40C_5v50 | 0.2824 | 0.2992 | 0.0168 (+5.9390%) ⭕ |
| clock__skew__worst_hold__corner:nom_ss_125C_4v50 | -0.3351 | -0.3756 | -0.0405 (+12.0923%) ⭕ |
| clock__skew__worst_setup__corner:nom_ss_125C_4v50 | 0.3350 | 0.3808 | 0.0458 (+13.6802%) ⭕ |
| design__max_slew_violation__count__corner:nom_ss_125C_4v50 | 59 | 41 | -18 (-30.5085%) ⭕ |
| clock__skew__worst_hold__corner:nom_tt_025C_5v00 | -0.2981 | -0.3227 | -0.0246 (+8.2568%) ⭕ |
| clock__skew__worst_setup__corner:nom_tt_025C_5v00 | 0.2984 | 0.3250 | 0.0266 (+8.9025%) ⭕ |
| antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
| design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count | 18 | 18 | 0 (0.0000%) ⭕ |
| ir__voltage__worst | 4.9900 | 4.9900 | 0.0000 (0.0000%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ff_n40C_5v50 | 18 | 18 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ss_125C_4v50 | 18 | 18 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_tt_025C_5v00 | 18 | 18 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ff_n40C_5v50 | 18 | 18 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ss_125C_4v50 | 18 | 18 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_tt_025C_5v00 | 18 | 18 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ff_n40C_5v50 | 18 | 18 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ss_125C_4v50 | 18 | 18 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_tt_025C_5v00 | 18 | 18 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
gf180mcuD/gf180mcu_fd_sc_mcu7t5v0/zipdiv
| Metric | Before | After | Delta |
|---|---|---|---|
| timing__setup__tns | -289.0041 | -299.8823 | -10.8782 (+3.7640%) |
| timing__setup__wns | -4.5464 | -4.6980 | -0.1516 (+3.3354%) |
| timing__setup_r2r_vio__count | 331 | 299 | -32 (-9.6677%) |
| timing__setup_vio__count | 369 | 363 | -6 (-1.6260%) |
| timing__setup__tns__corner:max_ss_125C_4v50 | -289.0041 | -299.8823 | -10.8782 (+3.7640%) |
| timing__setup__wns__corner:max_ss_125C_4v50 | -4.5464 | -4.6980 | -0.1516 (+3.3354%) |
| timing__setup_r2r_vio__count__corner:max_ss_125C_4v50 | 111 | 114 | 3 (+2.7027%) |
| timing__setup_vio__count__corner:max_ss_125C_4v50 | 127 | 130 | 3 (+2.3622%) |
| timing__setup__tns__corner:min_ss_125C_4v50 | -226.1739 | -230.5184 | -4.3444 (+1.9208%) |
| timing__setup__wns__corner:min_ss_125C_4v50 | -4.2418 | -4.4466 | -0.2048 (+4.8272%) |
| timing__setup_r2r_vio__count__corner:min_ss_125C_4v50 | 109 | 88 | -21 (-19.2661%) |
| timing__setup_vio__count__corner:min_ss_125C_4v50 | 116 | 115 | -1 (-0.8621%) |
| timing__setup__tns__corner:nom_ss_125C_4v50 | -254.1828 | -260.1193 | -5.9365 (+2.3355%) |
| timing__setup__wns__corner:nom_ss_125C_4v50 | -4.3646 | -4.5631 | -0.1985 (+4.5481%) |
| timing__setup_r2r_vio__count__corner:nom_ss_125C_4v50 | 111 | 97 | -14 (-12.6126%) |
| timing__setup_vio__count__corner:nom_ss_125C_4v50 | 126 | 118 | -8 (-6.3492%) |
| design__max_slew_violation__count | 59 | 128 | 69 (+116.9492%) ❗ |
| ir__drop__worst | 0.0016 | 0.0018 | 0.0002 (+12.5786%) ❗ |
| design__max_slew_violation__count__corner:max_ss_125C_4v50 | 59 | 128 | 69 (+116.9492%) ❗ |
| design__max_slew_violation__count__corner:min_ss_125C_4v50 | 54 | 79 | 25 (+46.2963%) ❗ |
| design__max_slew_violation__count__corner:nom_ss_125C_4v50 | 54 | 95 | 41 (+75.9259%) ❗ |
| clock__skew__worst_hold | -0.2646 | -0.2663 | -0.0016 (+0.6120%) ⭕ |
| clock__skew__worst_setup | 0.2645 | 0.2653 | 0.0009 (+0.3240%) ⭕ |
| design__core__area | 77773.7000 | 73916.8000 | -3856.9000 (-4.9591%) ⭕ |
| design__die__area | 91317 | 87589 | -3728 (-4.0825%) ⭕ |
| design__instance__area | 77773.7000 | 73916.8000 | -3856.9000 (-4.9591%) ⭕ |
| design__max_cap_violation__count | 3 | 1 | -2 (-66.6667%) ⭕ |
| ir__drop__avg | 0.0004 | 0.0003 | -0.0000 (-6.7797%) ⭕ |
| power__internal__total | 0.0191 | 0.0180 | -0.0012 (-6.0420%) ⭕ |
| power__leakage__total | 0.0000 | 0.0000 | -0.0000 (-4.0333%) ⭕ |
| power__switching__total | 0.0092 | 0.0085 | -0.0007 (-7.7424%) ⭕ |
| power__total | 0.0283 | 0.0264 | -0.0019 (-6.5929%) ⭕ |
| clock__skew__worst_hold__corner:max_ff_n40C_5v50 | -0.2689 | -0.2706 | -0.0016 (+0.6130%) ⭕ |
| clock__skew__worst_setup__corner:max_ff_n40C_5v50 | 0.2688 | 0.2700 | 0.0012 (+0.4460%) ⭕ |
| design__max_cap_violation__count__corner:max_ff_n40C_5v50 | 3 | 1 | -2 (-66.6667%) ⭕ |
| clock__skew__worst_hold__corner:max_ss_125C_4v50 | -0.3024 | -0.3036 | -0.0011 (+0.3792%) ⭕ |
| clock__skew__worst_setup__corner:max_ss_125C_4v50 | 0.3004 | 0.3023 | 0.0019 (+0.6320%) ⭕ |
| design__max_cap_violation__count__corner:max_ss_125C_4v50 | 3 | 1 | -2 (-66.6667%) ⭕ |
| clock__skew__worst_hold__corner:max_tt_025C_5v00 | -0.2794 | -0.2810 | -0.0015 (+0.5477%) ⭕ |
| clock__skew__worst_setup__corner:max_tt_025C_5v00 | 0.2784 | 0.2797 | 0.0013 (+0.4683%) ⭕ |
| design__max_cap_violation__count__corner:max_tt_025C_5v00 | 3 | 1 | -2 (-66.6667%) ⭕ |
| design__max_slew_violation__count__corner:max_tt_025C_5v00 | 11 | 0 | -11 (-100.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_ff_n40C_5v50 | -0.2646 | -0.2663 | -0.0016 (+0.6120%) ⭕ |
| clock__skew__worst_setup__corner:min_ff_n40C_5v50 | 0.2645 | 0.2653 | 0.0009 (+0.3240%) ⭕ |
| design__max_cap_violation__count__corner:min_ff_n40C_5v50 | 3 | 1 | -2 (-66.6667%) ⭕ |
| clock__skew__worst_hold__corner:min_ss_125C_4v50 | -0.2913 | -0.2932 | -0.0019 (+0.6578%) ⭕ |
| clock__skew__worst_setup__corner:min_ss_125C_4v50 | 0.2905 | 0.2922 | 0.0017 (+0.5915%) ⭕ |
| design__max_cap_violation__count__corner:min_ss_125C_4v50 | 3 | 1 | -2 (-66.6667%) ⭕ |
| clock__skew__worst_hold__corner:min_tt_025C_5v00 | -0.2730 | -0.2747 | -0.0017 (+0.6366%) ⭕ |
| clock__skew__worst_setup__corner:min_tt_025C_5v00 | 0.2726 | 0.2737 | 0.0011 (+0.4138%) ⭕ |
| design__max_cap_violation__count__corner:min_tt_025C_5v00 | 3 | 1 | -2 (-66.6667%) ⭕ |
| design__max_slew_violation__count__corner:min_tt_025C_5v00 | 11 | 0 | -11 (-100.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_ff_n40C_5v50 | -0.2666 | -0.2682 | -0.0016 (+0.6072%) ⭕ |
| clock__skew__worst_setup__corner:nom_ff_n40C_5v50 | 0.2665 | 0.2675 | 0.0010 (+0.3753%) ⭕ |
| design__max_cap_violation__count__corner:nom_ff_n40C_5v50 | 3 | 1 | -2 (-66.6667%) ⭕ |
| clock__skew__worst_hold__corner:nom_ss_125C_4v50 | -0.2964 | -0.2979 | -0.0015 (+0.5042%) ⭕ |
| clock__skew__worst_setup__corner:nom_ss_125C_4v50 | 0.2950 | 0.2968 | 0.0018 (+0.5973%) ⭕ |
| design__max_cap_violation__count__corner:nom_ss_125C_4v50 | 3 | 1 | -2 (-66.6667%) ⭕ |
| clock__skew__worst_hold__corner:nom_tt_025C_5v00 | -0.2759 | -0.2776 | -0.0016 (+0.5821%) ⭕ |
| clock__skew__worst_setup__corner:nom_tt_025C_5v00 | 0.2752 | 0.2764 | 0.0012 (+0.4315%) ⭕ |
| design__max_cap_violation__count__corner:nom_tt_025C_5v00 | 3 | 1 | -2 (-66.6667%) ⭕ |
| design__max_slew_violation__count__corner:nom_tt_025C_5v00 | 11 | 0 | -11 (-100.0000%) ⭕ |
| antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
| design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count | 1 | 1 | 0 (0.0000%) ⭕ |
| ir__voltage__worst | 5 | 5 | 0 (0.0000%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ff_n40C_5v50 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ff_n40C_5v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ss_125C_4v50 | 1 | 1 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ss_125C_4v50 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_tt_025C_5v00 | 1 | 1 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_tt_025C_5v00 | 0 | 0 | 0 (0.0000%) ⭕ |
ihp-sg13g2/sg13g2_stdcell/APU
| Metric | Before | After | Delta |
|---|---|---|---|
| antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold | -0.2653 | -0.2653 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup | 0.2650 | 0.2650 | 0.0000 (0.0000%) ⭕ |
| design__core__area | 135342 | 135342 | 0 (0.0000%) ⭕ |
| design__die__area | 152133 | 152133 | 0 (0.0000%) ⭕ |
| design__instance__area | 135342 | 135342 | 0 (0.0000%) ⭕ |
| design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count | 36 | 36 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| ir__drop__avg | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
| ir__drop__worst | 0.0007 | 0.0007 | 0.0000 (0.0000%) ⭕ |
| ir__voltage__worst | 1.2000 | 1.2000 | 0.0000 (0.0000%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| power__internal__total | 0.0018 | 0.0018 | 0.0000 (0.0000%) ⭕ |
| power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
| power__switching__total | 0.0005 | 0.0005 | 0.0000 (0.0000%) ⭕ |
| power__total | 0.0023 | 0.0023 | 0.0000 (0.0000%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_fast_1p32V_m40C | -0.2653 | -0.2653 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_fast_1p32V_m40C | 0.2650 | 0.2650 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_fast_1p32V_m40C | 36 | 36 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_slow_1p08V_125C | -0.2718 | -0.2718 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_slow_1p08V_125C | 0.2718 | 0.2718 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_slow_1p08V_125C | 36 | 36 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_typ_1p20V_25C | -0.2658 | -0.2658 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_typ_1p20V_25C | 0.2655 | 0.2655 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_typ_1p20V_25C | 36 | 36 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
ihp-sg13g2/sg13g2_stdcell/EF_GPIO
| Metric | Before | After | Delta |
|---|---|---|---|
| antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold | -0.2511 | -0.2511 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup | 0.2509 | 0.2509 | 0.0000 (0.0000%) ⭕ |
| design__core__area | 4287.4300 | 4287.4300 | 0.0000 (0.0000%) ⭕ |
| design__die__area | 6469.7700 | 6469.7700 | 0.0000 (0.0000%) ⭕ |
| design__instance__area | 4287.4300 | 4287.4300 | 0.0000 (0.0000%) ⭕ |
| design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| ir__drop__avg | 0.0002 | 0.0002 | 0.0000 (0.0000%) ⭕ |
| ir__drop__worst | 0.0009 | 0.0009 | 0.0000 (0.0000%) ⭕ |
| ir__voltage__worst | 1.2000 | 1.2000 | 0.0000 (0.0000%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| power__internal__total | 0.0002 | 0.0002 | 0.0000 (0.0000%) ⭕ |
| power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
| power__switching__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
| power__total | 0.0002 | 0.0002 | 0.0000 (0.0000%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_fast_1p32V_m40C | -0.2511 | -0.2511 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_fast_1p32V_m40C | 0.2513 | 0.2513 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_slow_1p08V_125C | -0.2517 | -0.2517 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_slow_1p08V_125C | 0.2509 | 0.2509 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_typ_1p20V_25C | -0.2513 | -0.2513 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_typ_1p20V_25C | 0.2511 | 0.2511 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
ihp-sg13g2/sg13g2_stdcell/EF_PSRAM_CTRL_V2
| Metric | Before | After | Delta |
|---|---|---|---|
| antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold | -0.2560 | -0.2560 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup | 0.2554 | 0.2554 | 0.0000 (0.0000%) ⭕ |
| design__core__area | 13172.5000 | 13172.5000 | 0.0000 (0.0000%) ⭕ |
| design__die__area | 18734.9000 | 18734.9000 | 0.0000 (0.0000%) ⭕ |
| design__instance__area | 13172.5000 | 13172.5000 | 0.0000 (0.0000%) ⭕ |
| design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| ir__drop__avg | 0.0003 | 0.0003 | 0.0000 (0.0000%) ⭕ |
| ir__drop__worst | 0.0024 | 0.0024 | 0.0000 (0.0000%) ⭕ |
| ir__voltage__worst | 1.2000 | 1.2000 | 0.0000 (0.0000%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| power__internal__total | 0.0006 | 0.0006 | 0.0000 (0.0000%) ⭕ |
| power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
| power__switching__total | 0.0003 | 0.0003 | 0.0000 (0.0000%) ⭕ |
| power__total | 0.0009 | 0.0009 | 0.0000 (0.0000%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_fast_1p32V_m40C | -0.2565 | -0.2565 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_fast_1p32V_m40C | 0.2557 | 0.2557 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_slow_1p08V_125C | -0.2560 | -0.2560 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_slow_1p08V_125C | 0.2554 | 0.2554 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_typ_1p20V_25C | -0.2563 | -0.2563 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_typ_1p20V_25C | 0.2556 | 0.2556 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
ihp-sg13g2/sg13g2_stdcell/blink
| Metric | Before | After | Delta |
|---|---|---|---|
| clock__skew__worst_hold | -0.2530 | -0.2520 | 0.0010 (-0.3989%) ❗ |
| clock__skew__worst_setup | 0.2532 | 0.2520 | -0.0012 (-0.4670%) ❗ |
| power__internal__total | 0.0002 | 0.0002 | 0.0000 (+0.0006%) ❗ |
| power__leakage__total | 0.0000 | 0.0000 | 0.0000 (+0.9206%) ❗ |
| clock__skew__worst_hold__corner:nom_fast_1p32V_m40C | -0.2534 | -0.2520 | 0.0014 (-0.5646%) ❗ |
| clock__skew__worst_setup__corner:nom_fast_1p32V_m40C | 0.2536 | 0.2520 | -0.0016 (-0.6403%) ❗ |
| clock__skew__worst_hold__corner:nom_slow_1p08V_125C | -0.2530 | -0.2520 | 0.0009 (-0.3736%) ❗ |
| clock__skew__worst_setup__corner:nom_slow_1p08V_125C | 0.2532 | 0.2520 | -0.0011 (-0.4418%) ❗ |
| clock__skew__worst_hold__corner:nom_typ_1p20V_25C | -0.2532 | -0.2520 | 0.0012 (-0.4881%) ❗ |
| clock__skew__worst_setup__corner:nom_typ_1p20V_25C | 0.2534 | 0.2520 | -0.0014 (-0.5598%) ❗ |
| design__core__area | 4225.7400 | 4194.8900 | -30.8500 (-0.7300%) ⭕ |
| design__die__area | 7458.7900 | 7396.3700 | -62.4200 (-0.8369%) ⭕ |
| design__instance__area | 4225.7400 | 4194.8900 | -30.8500 (-0.7300%) ⭕ |
| ir__drop__avg | 0.0007 | 0.0005 | -0.0002 (-23.4870%) ⭕ |
| ir__drop__worst | 0.0040 | 0.0025 | -0.0015 (-38.2134%) ⭕ |
| power__switching__total | 0.0000 | 0.0000 | -0.0000 (-1.0579%) ⭕ |
| power__total | 0.0002 | 0.0002 | -0.0000 (-0.1265%) ⭕ |
| antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| ir__voltage__worst | 1.2000 | 1.2000 | 0.0000 (0.0000%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
ihp-sg13g2/sg13g2_stdcell/cell_inverter
| Metric | Before | After | Delta |
|---|---|---|---|
| design__instance__area | 5.4432 | 5.4432 | 0.0000 (0.0000%) ⭕ |
| design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
ihp-sg13g2/sg13g2_stdcell/full_chip
| Metric | Before | After | Delta |
|---|---|---|---|
| antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold | -0.2513 | -0.2513 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup | 0.2511 | 0.2511 | 0.0000 (0.0000%) ⭕ |
| design__core__area | 752466 | 752466 | 0 (0.0000%) ⭕ |
| design__die__area | 2560000 | 2560000 | 0 (0.0000%) ⭕ |
| design__instance__area | 1769270 | 1769270 | 0 (0.0000%) ⭕ |
| design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count | 16 | 16 | 0 (0.0000%) ⭕ |
| ir__drop__avg | 0.0005 | 0.0005 | 0.0000 (0.0000%) ⭕ |
| ir__drop__worst | 0.0007 | 0.0007 | 0.0000 (0.0000%) ⭕ |
| ir__voltage__worst | 1.2000 | 1.2000 | 0.0000 (0.0000%) ⭕ |
| power__internal__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
| power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
| power__switching__total | 0.0033 | 0.0033 | 0.0000 (0.0000%) ⭕ |
| power__total | 0.0034 | 0.0034 | 0.0000 (0.0000%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_fast_1p32V_m40C | -0.2516 | -0.2516 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_fast_1p32V_m40C | 0.2514 | 0.2514 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_fast_1p32V_m40C | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_slow_1p08V_125C | -0.2513 | -0.2513 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_slow_1p08V_125C | 0.2511 | 0.2511 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_slow_1p08V_125C | 16 | 16 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_typ_1p20V_25C | -0.2514 | -0.2514 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_typ_1p20V_25C | 0.2512 | 0.2512 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_typ_1p20V_25C | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
ihp-sg13g2/sg13g2_stdcell/hold_violations_1
| Metric | Before | After | Delta |
|---|---|---|---|
| antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold | -0.2534 | -0.2534 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup | 0.2526 | 0.2526 | 0.0000 (0.0000%) ⭕ |
| design__core__area | 5842.3700 | 5842.3700 | 0.0000 (0.0000%) ⭕ |
| design__die__area | 9582.1600 | 9582.1600 | 0.0000 (0.0000%) ⭕ |
| design__instance__area | 5842.3700 | 5842.3700 | 0.0000 (0.0000%) ⭕ |
| design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| ir__drop__avg | 0.0003 | 0.0003 | 0.0000 (0.0000%) ⭕ |
| ir__drop__worst | 0.0030 | 0.0030 | 0.0000 (0.0000%) ⭕ |
| ir__voltage__worst | 1.2000 | 1.2000 | 0.0000 (0.0000%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| power__internal__total | 0.0003 | 0.0003 | 0.0000 (0.0000%) ⭕ |
| power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
| power__switching__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
| power__total | 0.0003 | 0.0003 | 0.0000 (0.0000%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns | -3.7788 | -3.7788 | 0.0000 (0.0000%) ⭕ |
| timing__hold__wns | -0.1267 | -0.1267 | 0.0000 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count | 62 | 62 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count | 62 | 62 | 0 (0.0000%) ⭕ |
| timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_fast_1p32V_m40C | -0.2543 | -0.2543 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_fast_1p32V_m40C | 0.2533 | 0.2533 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_fast_1p32V_m40C | -3.7788 | -3.7788 | 0.0000 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_fast_1p32V_m40C | -0.1267 | -0.1267 | 0.0000 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_fast_1p32V_m40C | 31 | 31 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_fast_1p32V_m40C | 31 | 31 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_slow_1p08V_125C | -0.2534 | -0.2534 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_slow_1p08V_125C | 0.2526 | 0.2526 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_typ_1p20V_25C | -0.2539 | -0.2539 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_typ_1p20V_25C | 0.2530 | 0.2530 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_typ_1p20V_25C | -1.7952 | -1.7952 | 0.0000 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_typ_1p20V_25C | -0.0625 | -0.0625 | 0.0000 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_typ_1p20V_25C | 31 | 31 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_typ_1p20V_25C | 31 | 31 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
ihp-sg13g2/sg13g2_stdcell/hold_violations_2
| Metric | Before | After | Delta |
|---|---|---|---|
| antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold | -0.2534 | -0.2534 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup | 0.2526 | 0.2526 | 0.0000 (0.0000%) ⭕ |
| design__core__area | 5842.3700 | 5842.3700 | 0.0000 (0.0000%) ⭕ |
| design__die__area | 9582.1600 | 9582.1600 | 0.0000 (0.0000%) ⭕ |
| design__instance__area | 5842.3700 | 5842.3700 | 0.0000 (0.0000%) ⭕ |
| design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| ir__drop__avg | 0.0003 | 0.0003 | 0.0000 (0.0000%) ⭕ |
| ir__drop__worst | 0.0030 | 0.0030 | 0.0000 (0.0000%) ⭕ |
| ir__voltage__worst | 1.2000 | 1.2000 | 0.0000 (0.0000%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| power__internal__total | 0.0003 | 0.0003 | 0.0000 (0.0000%) ⭕ |
| power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
| power__switching__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
| power__total | 0.0003 | 0.0003 | 0.0000 (0.0000%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns | -4.1361 | -4.1361 | 0.0000 (0.0000%) ⭕ |
| timing__hold__wns | -0.4950 | -0.4950 | 0.0000 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count | 62 | 62 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count | 65 | 65 | 0 (0.0000%) ⭕ |
| timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_fast_1p32V_m40C | -0.2543 | -0.2543 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_fast_1p32V_m40C | 0.2533 | 0.2533 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_fast_1p32V_m40C | -4.1361 | -4.1361 | 0.0000 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_fast_1p32V_m40C | -0.3573 | -0.3573 | 0.0000 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_fast_1p32V_m40C | 31 | 31 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_fast_1p32V_m40C | 32 | 32 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_slow_1p08V_125C | -0.2534 | -0.2534 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_slow_1p08V_125C | 0.2526 | 0.2526 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_slow_1p08V_125C | -0.4950 | -0.4950 | 0.0000 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_slow_1p08V_125C | -0.4950 | -0.4950 | 0.0000 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_slow_1p08V_125C | 1 | 1 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_typ_1p20V_25C | -0.2539 | -0.2539 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_typ_1p20V_25C | 0.2530 | 0.2530 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_typ_1p20V_25C | -2.1999 | -2.1999 | 0.0000 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_typ_1p20V_25C | -0.4047 | -0.4047 | 0.0000 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_typ_1p20V_25C | 31 | 31 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_typ_1p20V_25C | 32 | 32 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
ihp-sg13g2/sg13g2_stdcell/hold_violations_3
| Metric | Before | After | Delta |
|---|---|---|---|
| antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold | -0.2519 | -0.2519 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup | 0.2519 | 0.2519 | 0.0000 (0.0000%) ⭕ |
| design__core__area | 15355.3000 | 15355.3000 | 0.0000 (0.0000%) ⭕ |
| design__die__area | 18225 | 18225 | 0 (0.0000%) ⭕ |
| design__instance__area | 13061.1000 | 13061.1000 | 0.0000 (0.0000%) ⭕ |
| design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| ir__drop__avg | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
| ir__drop__worst | 0.0003 | 0.0003 | 0.0000 (0.0000%) ⭕ |
| ir__voltage__worst | 1.2000 | 1.2000 | 0.0000 (0.0000%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| power__internal__total | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
| power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
| power__switching__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
| power__total | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns | -0.3278 | -0.3278 | 0.0000 (0.0000%) ⭕ |
| timing__hold__wns | -0.1141 | -0.1141 | 0.0000 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count | 6 | 6 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count | 6 | 6 | 0 (0.0000%) ⭕ |
| timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_fast_1p32V_m40C | -0.2519 | -0.2519 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_fast_1p32V_m40C | 0.2519 | 0.2519 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_fast_1p32V_m40C | -0.3278 | -0.3278 | 0.0000 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_fast_1p32V_m40C | -0.1141 | -0.1141 | 0.0000 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_fast_1p32V_m40C | 3 | 3 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_fast_1p32V_m40C | 3 | 3 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_slow_1p08V_125C | -0.2522 | -0.2522 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_slow_1p08V_125C | 0.2522 | 0.2522 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_typ_1p20V_25C | -0.2520 | -0.2520 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_typ_1p20V_25C | 0.2520 | 0.2520 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_typ_1p20V_25C | -0.1156 | -0.1156 | 0.0000 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_typ_1p20V_25C | -0.0448 | -0.0448 | 0.0000 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_typ_1p20V_25C | 3 | 3 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_typ_1p20V_25C | 3 | 3 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
ihp-sg13g2/sg13g2_stdcell/inverter
| Metric | Before | After | Delta |
|---|---|---|---|
| antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
| design__core__area | 725.7600 | 725.7600 | 0.0000 (0.0000%) ⭕ |
| design__die__area | 2500 | 2500 | 0 (0.0000%) ⭕ |
| design__instance__area | 725.7600 | 725.7600 | 0.0000 (0.0000%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
ihp-sg13g2/sg13g2_stdcell/latch_bad
| Metric | Before | After | Delta |
|---|---|---|---|
| design__instance__area | 30.8448 | 30.8448 | 0.0000 (0.0000%) ⭕ |
| design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
ihp-sg13g2/sg13g2_stdcell/latch_good
| Metric | Before | After | Delta |
|---|---|---|---|
| design__instance__area | 30.8448 | 30.8448 | 0.0000 (0.0000%) ⭕ |
| design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
ihp-sg13g2/sg13g2_stdcell/non_const_async_reset
| Metric | Before | After | Delta |
|---|---|---|---|
| design__instance__area | 10.8864 | 10.8864 | 0.0000 (0.0000%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
ihp-sg13g2/sg13g2_stdcell/s44
| Metric | Before | After | Delta |
|---|---|---|---|
| antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold | -0.2613 | -0.2613 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup | 0.2520 | 0.2520 | 0.0000 (0.0000%) ⭕ |
| design__core__area | 70743.5000 | 70743.5000 | 0.0000 (0.0000%) ⭕ |
| design__die__area | 83147.5000 | 83147.5000 | 0.0000 (0.0000%) ⭕ |
| design__instance__area | 70743.5000 | 70743.5000 | 0.0000 (0.0000%) ⭕ |
| design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| ir__drop__avg | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
| ir__drop__worst | 0.0003 | 0.0003 | 0.0000 (0.0000%) ⭕ |
| ir__voltage__worst | 1.2000 | 1.2000 | 0.0000 (0.0000%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| power__internal__total | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
| power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
| power__switching__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
| power__total | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_fast_1p32V_m40C | -0.2636 | -0.2636 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_fast_1p32V_m40C | 0.2521 | 0.2521 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_slow_1p08V_125C | -0.2613 | -0.2613 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_slow_1p08V_125C | 0.2521 | 0.2521 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_typ_1p20V_25C | -0.2626 | -0.2626 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_typ_1p20V_25C | 0.2520 | 0.2520 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
ihp-sg13g2/sg13g2_stdcell/spm
| Metric | Before | After | Delta |
|---|---|---|---|
| antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold | -0.2608 | -0.2608 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup | 0.2611 | 0.2611 | 0.0000 (0.0000%) ⭕ |
| design__core__area | 10532.6000 | 10532.6000 | 0.0000 (0.0000%) ⭕ |
| design__die__area | 15417.6000 | 15417.6000 | 0.0000 (0.0000%) ⭕ |
| design__instance__area | 10075.4000 | 10075.4000 | 0.0000 (0.0000%) ⭕ |
| design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| ir__drop__avg | 0.0003 | 0.0003 | 0.0000 (0.0000%) ⭕ |
| ir__drop__worst | 0.0022 | 0.0022 | 0.0000 (0.0000%) ⭕ |
| ir__voltage__worst | 1.2000 | 1.2000 | 0.0000 (0.0000%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| power__internal__total | 0.0010 | 0.0010 | 0.0000 (0.0000%) ⭕ |
| power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
| power__switching__total | 0.0002 | 0.0002 | 0.0000 (0.0000%) ⭕ |
| power__total | 0.0012 | 0.0012 | 0.0000 (0.0000%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_fast_1p32V_m40C | -0.2614 | -0.2614 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_fast_1p32V_m40C | 0.2636 | 0.2636 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_fast_1p32V_m40C | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_slow_1p08V_125C | -0.2610 | -0.2610 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_slow_1p08V_125C | 0.2611 | 0.2611 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_slow_1p08V_125C | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_typ_1p20V_25C | -0.2608 | -0.2608 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_typ_1p20V_25C | 0.2624 | 0.2624 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_typ_1p20V_25C | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
ihp-sg13g2/sg13g2_stdcell/usb
| Metric | Before | After | Delta |
|---|---|---|---|
| antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold | -0.2572 | -0.2572 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup | 0.2569 | 0.2569 | 0.0000 (0.0000%) ⭕ |
| design__core__area | 38966.1000 | 38966.1000 | 0.0000 (0.0000%) ⭕ |
| design__die__area | 48046.6000 | 48046.6000 | 0.0000 (0.0000%) ⭕ |
| design__instance__area | 38966.1000 | 38966.1000 | 0.0000 (0.0000%) ⭕ |
| design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| ir__drop__avg | 0.0003 | 0.0003 | 0.0000 (0.0000%) ⭕ |
| ir__drop__worst | 0.0025 | 0.0025 | 0.0000 (0.0000%) ⭕ |
| ir__voltage__worst | 1.2000 | 1.2000 | 0.0000 (0.0000%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| power__internal__total | 0.0022 | 0.0022 | 0.0000 (0.0000%) ⭕ |
| power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
| power__switching__total | 0.0005 | 0.0005 | 0.0000 (0.0000%) ⭕ |
| power__total | 0.0027 | 0.0027 | 0.0000 (0.0000%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_fast_1p32V_m40C | -0.2572 | -0.2572 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_fast_1p32V_m40C | 0.2569 | 0.2569 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_fast_1p32V_m40C | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_slow_1p08V_125C | -0.2589 | -0.2589 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_slow_1p08V_125C | 0.2580 | 0.2580 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_slow_1p08V_125C | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_typ_1p20V_25C | -0.2575 | -0.2575 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_typ_1p20V_25C | 0.2570 | 0.2570 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_typ_1p20V_25C | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
ihp-sg13g2/sg13g2_stdcell/usb_cdc_core
| Metric | Before | After | Delta |
|---|---|---|---|
| antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold | -0.2692 | -0.2692 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup | 0.2690 | 0.2690 | 0.0000 (0.0000%) ⭕ |
| design__core__area | 57039.3000 | 57039.3000 | 0.0000 (0.0000%) ⭕ |
| design__die__area | 67910.8000 | 67910.8000 | 0.0000 (0.0000%) ⭕ |
| design__instance__area | 57039.3000 | 57039.3000 | 0.0000 (0.0000%) ⭕ |
| design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count | 23 | 23 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| ir__drop__avg | 0.0003 | 0.0003 | 0.0000 (0.0000%) ⭕ |
| ir__drop__worst | 0.0038 | 0.0038 | 0.0000 (0.0000%) ⭕ |
| ir__voltage__worst | 1.2000 | 1.2000 | 0.0000 (0.0000%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| power__internal__total | 0.0023 | 0.0023 | 0.0000 (0.0000%) ⭕ |
| power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
| power__switching__total | 0.0005 | 0.0005 | 0.0000 (0.0000%) ⭕ |
| power__total | 0.0028 | 0.0028 | 0.0000 (0.0000%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_fast_1p32V_m40C | -0.2692 | -0.2692 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_fast_1p32V_m40C | 0.2690 | 0.2690 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_fast_1p32V_m40C | 23 | 23 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_slow_1p08V_125C | -0.2832 | -0.2832 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_slow_1p08V_125C | 0.2812 | 0.2812 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_slow_1p08V_125C | 23 | 23 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_typ_1p20V_25C | -0.2747 | -0.2747 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_typ_1p20V_25C | 0.2738 | 0.2738 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_typ_1p20V_25C | 23 | 23 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
ihp-sg13g2/sg13g2_stdcell/wbqspiflash
| Metric | Before | After | Delta |
|---|---|---|---|
| clock__skew__worst_hold | -0.2681 | -0.2657 | 0.0024 (-0.8919%) ❗ |
| ir__drop__avg | 0.0004 | 0.0005 | 0.0001 (+19.1847%) ❗ |
| ir__drop__worst | 0.0035 | 0.0050 | 0.0015 (+43.7143%) ❗ |
| ir__voltage__worst | 1.2000 | 1.1900 | -0.0100 (-0.8333%) ❗ |
| power__internal__total | 0.0040 | 0.0040 | 0.0000 (+0.5349%) ❗ |
| clock__skew__worst_hold__corner:nom_fast_1p32V_m40C | -0.2681 | -0.2657 | 0.0024 (-0.8919%) ❗ |
| clock__skew__worst_hold__corner:nom_typ_1p20V_25C | -0.2690 | -0.2679 | 0.0012 (-0.4309%) ❗ |
| clock__skew__worst_setup | 0.2645 | 0.2670 | 0.0026 (+0.9686%) ⭕ |
| design__core__area | 63108 | 62869 | -239 (-0.3787%) ⭕ |
| design__die__area | 74936.3000 | 74616.2000 | -320.1000 (-0.4272%) ⭕ |
| design__instance__area | 63108 | 62869 | -239 (-0.3787%) ⭕ |
| design__max_fanout_violation__count | 23 | 22 | -1 (-4.3478%) ⭕ |
| power__leakage__total | 0.0000 | 0.0000 | -0.0000 (-0.3129%) ⭕ |
| power__switching__total | 0.0021 | 0.0020 | -0.0001 (-2.5124%) ⭕ |
| power__total | 0.0060 | 0.0060 | -0.0000 (-0.5105%) ⭕ |
| clock__skew__worst_setup__corner:nom_fast_1p32V_m40C | 0.2645 | 0.2670 | 0.0026 (+0.9686%) ⭕ |
| design__max_fanout_violation__count__corner:nom_fast_1p32V_m40C | 23 | 22 | -1 (-4.3478%) ⭕ |
| clock__skew__worst_hold__corner:nom_slow_1p08V_125C | -0.2703 | -0.2728 | -0.0025 (+0.9111%) ⭕ |
| clock__skew__worst_setup__corner:nom_slow_1p08V_125C | 0.2675 | 0.2826 | 0.0150 (+5.6255%) ⭕ |
| design__max_fanout_violation__count__corner:nom_slow_1p08V_125C | 23 | 22 | -1 (-4.3478%) ⭕ |
| clock__skew__worst_setup__corner:nom_typ_1p20V_25C | 0.2655 | 0.2732 | 0.0077 (+2.8975%) ⭕ |
| design__max_fanout_violation__count__corner:nom_typ_1p20V_25C | 23 | 22 | -1 (-4.3478%) ⭕ |
| antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
| design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
ihp-sg13g2/sg13g2_stdcell/xtea
| Metric | Before | After | Delta |
|---|---|---|---|
| clock__skew__worst_hold__corner:nom_fast_1p32V_m40C | -0.2524 | -0.2519 | 0.0005 (-0.2060%) ❗ |
| clock__skew__worst_setup__corner:nom_fast_1p32V_m40C | 0.2519 | 0.2516 | -0.0003 (-0.1264%) ❗ |
| clock__skew__worst_hold__corner:nom_typ_1p20V_25C | -0.2522 | -0.2519 | 0.0003 (-0.1044%) ❗ |
| clock__skew__worst_hold | -0.2519 | -0.2519 | -0.0000 (+0.0032%) ⭕ |
| clock__skew__worst_setup | 0.2515 | 0.2516 | 0.0000 (+0.0180%) ⭕ |
| design__core__area | 4637.6100 | 4349.1200 | -288.4900 (-6.2207%) ⭕ |
| design__die__area | 7858.3300 | 7782.7400 | -75.5900 (-0.9619%) ⭕ |
| design__instance__area | 4637.6100 | 4349.1200 | -288.4900 (-6.2207%) ⭕ |
| ir__drop__avg | 0.0005 | 0.0003 | -0.0002 (-45.3211%) ⭕ |
| ir__drop__worst | 0.0044 | 0.0008 | -0.0036 (-82.6484%) ⭕ |
| power__internal__total | 0.0003 | 0.0003 | -0.0000 (-0.2404%) ⭕ |
| power__leakage__total | 0.0000 | 0.0000 | -0.0000 (-15.1050%) ⭕ |
| power__switching__total | 0.0001 | 0.0001 | -0.0000 (-2.1888%) ⭕ |
| power__total | 0.0004 | 0.0004 | -0.0000 (-0.5583%) ⭕ |
| clock__skew__worst_hold__corner:nom_slow_1p08V_125C | -0.2519 | -0.2520 | -0.0001 (+0.0470%) ⭕ |
| clock__skew__worst_setup__corner:nom_slow_1p08V_125C | 0.2515 | 0.2519 | 0.0003 (+0.1357%) ⭕ |
| clock__skew__worst_setup__corner:nom_typ_1p20V_25C | 0.2517 | 0.2517 | 0.0000 (+0.0019%) ⭕ |
| antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
| design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| ir__voltage__worst | 1.2000 | 1.2000 | 0.0000 (0.0000%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
ihp-sg13g2/sg13g2_stdcell/zipdiv
| Metric | Before | After | Delta |
|---|---|---|---|
| clock__skew__worst_hold | -0.2713 | -0.2561 | 0.0153 (-5.6247%) ❗ |
| clock__skew__worst_setup | 0.2750 | 0.2556 | -0.0193 (-7.0360%) ❗ |
| ir__drop__avg | 0.0002 | 0.0002 | 0.0000 (+2.2222%) ❗ |
| ir__drop__worst | 0.0017 | 0.0043 | 0.0026 (+148.2759%) ❗ |
| power__internal__total | 0.0015 | 0.0015 | 0.0000 (+0.0217%) ❗ |
| clock__skew__worst_hold__corner:nom_fast_1p32V_m40C | -0.2735 | -0.2561 | 0.0175 (-6.3829%) ❗ |
| clock__skew__worst_setup__corner:nom_fast_1p32V_m40C | 0.2751 | 0.2558 | -0.0193 (-7.0210%) ❗ |
| clock__skew__worst_hold__corner:nom_slow_1p08V_125C | -0.2713 | -0.2570 | 0.0144 (-5.2929%) ❗ |
| clock__skew__worst_setup__corner:nom_slow_1p08V_125C | 0.2752 | 0.2562 | -0.0189 (-6.8729%) ❗ |
| clock__skew__worst_hold__corner:nom_typ_1p20V_25C | -0.2725 | -0.2563 | 0.0162 (-5.9437%) ❗ |
| clock__skew__worst_setup__corner:nom_typ_1p20V_25C | 0.2750 | 0.2556 | -0.0193 (-7.0360%) ❗ |
| design__core__area | 34851.0000 | 34762.1000 | -88.9000 (-0.2551%) ⭕ |
| design__die__area | 43639.4000 | 43524.4000 | -115.0000 (-0.2635%) ⭕ |
| design__instance__area | 34851.0000 | 34762.1000 | -88.9000 (-0.2551%) ⭕ |
| power__leakage__total | 0.0000 | 0.0000 | -0.0000 (-0.4926%) ⭕ |
| power__switching__total | 0.0004 | 0.0004 | -0.0000 (-0.0894%) ⭕ |
| power__total | 0.0019 | 0.0019 | -0.0000 (-0.0007%) ⭕ |
| antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
| design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| ir__voltage__worst | 1.2000 | 1.2000 | 0.0000 (0.0000%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_fast_1p32V_m40C | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_fast_1p32V_m40C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_slow_1p08V_125C | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_slow_1p08V_125C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_typ_1p20V_25C | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_typ_1p20V_25C | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/APU
| Metric | Before | After | Delta |
|---|---|---|---|
| antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold | -0.2668 | -0.2668 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup | 0.2786 | 0.2786 | 0.0000 (0.0000%) ⭕ |
| design__core__area | 81978.6000 | 81978.6000 | 0.0000 (0.0000%) ⭕ |
| design__die__area | 92068.3000 | 92068.3000 | 0.0000 (0.0000%) ⭕ |
| design__instance__area | 81978.6000 | 81978.6000 | 0.0000 (0.0000%) ⭕ |
| design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count | 44 | 44 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count | 317 | 317 | 0 (0.0000%) ⭕ |
| ir__drop__avg | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
| ir__drop__worst | 0.0005 | 0.0005 | 0.0000 (0.0000%) ⭕ |
| ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| power__internal__total | 0.0021 | 0.0021 | 0.0000 (0.0000%) ⭕ |
| power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
| power__switching__total | 0.0010 | 0.0010 | 0.0000 (0.0000%) ⭕ |
| power__total | 0.0031 | 0.0031 | 0.0000 (0.0000%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns | -14.2157 | -14.2157 | 0.0000 (0.0000%) ⭕ |
| timing__setup__wns | -1.2685 | -1.2685 | 0.0000 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count | 51 | 51 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count | 56 | 56 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.2668 | -0.2668 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.2826 | 0.2826 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 44 | 44 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.3030 | -0.3030 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.3284 | 0.3284 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 44 | 44 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ss_100C_1v60 | 317 | 317 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ss_100C_1v60 | -14.2157 | -14.2157 | 0.0000 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ss_100C_1v60 | -1.2685 | -1.2685 | 0.0000 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 20 | 20 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ss_100C_1v60 | 23 | 23 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.2768 | -0.2768 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.2953 | 0.2953 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 44 | 44 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_tt_025C_1v80 | 7 | 7 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.2703 | -0.2703 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.2786 | 0.2786 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 44 | 44 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.3041 | -0.3041 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.3202 | 0.3202 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 44 | 44 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ss_100C_1v60 | 122 | 122 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ss_100C_1v60 | -4.0444 | -4.0444 | 0.0000 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ss_100C_1v60 | -0.6212 | -0.6212 | 0.0000 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 12 | 12 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ss_100C_1v60 | 12 | 12 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.2793 | -0.2793 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.2897 | 0.2897 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 44 | 44 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.2703 | -0.2703 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.2804 | 0.2804 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 44 | 44 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.3060 | -0.3060 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.3244 | 0.3244 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 44 | 44 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 200 | 200 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ss_100C_1v60 | -8.4877 | -8.4877 | 0.0000 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ss_100C_1v60 | -0.9513 | -0.9513 | 0.0000 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 19 | 19 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ss_100C_1v60 | 21 | 21 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.2800 | -0.2800 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.2925 | 0.2925 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 44 | 44 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 7 | 7 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/EF_GPIO
| Metric | Before | After | Delta |
|---|---|---|---|
| antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold | -0.2516 | -0.2516 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup | 0.2516 | 0.2516 | 0.0000 (0.0000%) ⭕ |
| design__core__area | 1981.9000 | 1981.9000 | 0.0000 (0.0000%) ⭕ |
| design__die__area | 3233.6200 | 3233.6200 | 0.0000 (0.0000%) ⭕ |
| design__instance__area | 1981.9000 | 1981.9000 | 0.0000 (0.0000%) ⭕ |
| design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| ir__drop__avg | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
| ir__drop__worst | 0.0002 | 0.0002 | 0.0000 (0.0000%) ⭕ |
| ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| power__internal__total | 0.0002 | 0.0002 | 0.0000 (0.0000%) ⭕ |
| power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
| power__switching__total | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
| power__total | 0.0003 | 0.0003 | 0.0000 (0.0000%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.2518 | -0.2518 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.2521 | 0.2521 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.2539 | -0.2539 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.2542 | 0.2542 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.2526 | -0.2526 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.2529 | 0.2529 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.2516 | -0.2516 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.2516 | 0.2516 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.2532 | -0.2532 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.2532 | 0.2532 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.2522 | -0.2522 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.2522 | 0.2522 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.2517 | -0.2517 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.2519 | 0.2519 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.2535 | -0.2535 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.2537 | 0.2537 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.2524 | -0.2524 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.2525 | 0.2525 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/EF_PSRAM_CTRL_V2
| Metric | Before | After | Delta |
|---|---|---|---|
| antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold | -0.2530 | -0.2530 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup | 0.2532 | 0.2532 | 0.0000 (0.0000%) ⭕ |
| design__core__area | 8720.8600 | 8720.8600 | 0.0000 (0.0000%) ⭕ |
| design__die__area | 12228 | 12228 | 0 (0.0000%) ⭕ |
| design__instance__area | 8720.8600 | 8720.8600 | 0.0000 (0.0000%) ⭕ |
| design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count | 78 | 78 | 0 (0.0000%) ⭕ |
| ir__drop__avg | 0.0004 | 0.0004 | 0.0000 (0.0000%) ⭕ |
| ir__drop__worst | 0.0008 | 0.0008 | 0.0000 (0.0000%) ⭕ |
| ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| power__internal__total | 0.0011 | 0.0011 | 0.0000 (0.0000%) ⭕ |
| power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
| power__switching__total | 0.0011 | 0.0011 | 0.0000 (0.0000%) ⭕ |
| power__total | 0.0022 | 0.0022 | 0.0000 (0.0000%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns | -2.6276 | -2.6276 | 0.0000 (0.0000%) ⭕ |
| timing__setup__wns | -0.9788 | -0.9788 | 0.0000 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count | 9 | 9 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.2530 | -0.2530 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.2532 | 0.2532 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.2581 | -0.2581 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.2581 | 0.2581 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ss_100C_1v60 | 78 | 78 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ss_100C_1v60 | -2.6276 | -2.6276 | 0.0000 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ss_100C_1v60 | -0.9788 | -0.9788 | 0.0000 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ss_100C_1v60 | 3 | 3 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.2548 | -0.2548 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.2548 | 0.2548 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.2533 | -0.2533 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.2533 | 0.2533 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.2575 | -0.2575 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.2575 | 0.2575 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ss_100C_1v60 | 13 | 13 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ss_100C_1v60 | -1.8043 | -1.8043 | 0.0000 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ss_100C_1v60 | -0.6865 | -0.6865 | 0.0000 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ss_100C_1v60 | 3 | 3 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.2547 | -0.2547 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.2548 | 0.2548 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.2532 | -0.2532 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.2532 | 0.2532 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.2579 | -0.2579 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.2579 | 0.2579 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 37 | 37 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ss_100C_1v60 | -2.2315 | -2.2315 | 0.0000 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ss_100C_1v60 | -0.8326 | -0.8326 | 0.0000 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ss_100C_1v60 | 3 | 3 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.2549 | -0.2549 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.2549 | 0.2549 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/EF_TCC32
| Metric | Before | After | Delta |
|---|---|---|---|
| antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold | -0.1133 | -0.1133 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup | 0.1132 | 0.1132 | 0.0000 (0.0000%) ⭕ |
| design__core__area | 14478.9000 | 14478.9000 | 0.0000 (0.0000%) ⭕ |
| design__die__area | 18938.1000 | 18938.1000 | 0.0000 (0.0000%) ⭕ |
| design__instance__area | 14478.9000 | 14478.9000 | 0.0000 (0.0000%) ⭕ |
| design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| ir__drop__avg | 0.0005 | 0.0005 | 0.0000 (0.0000%) ⭕ |
| ir__drop__worst | 0.0012 | 0.0012 | 0.0000 (0.0000%) ⭕ |
| ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| power__internal__total | 0.0015 | 0.0015 | 0.0000 (0.0000%) ⭕ |
| power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
| power__switching__total | 0.0012 | 0.0012 | 0.0000 (0.0000%) ⭕ |
| power__total | 0.0026 | 0.0026 | 0.0000 (0.0000%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns | -16.1419 | -16.1419 | 0.0000 (0.0000%) ⭕ |
| timing__setup__wns | -0.9546 | -0.9546 | 0.0000 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count | 96 | 96 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.1197 | -0.1197 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.1194 | 0.1194 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.1388 | -0.1388 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.1386 | 0.1386 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ss_100C_1v60 | -16.1419 | -16.1419 | 0.0000 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ss_100C_1v60 | -0.9546 | -0.9546 | 0.0000 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ss_100C_1v60 | 34 | 34 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.1249 | -0.1249 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.1247 | 0.1247 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.1133 | -0.1133 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.1132 | 0.1132 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.1299 | -0.1299 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.1298 | 0.1298 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ss_100C_1v60 | -7.2251 | -7.2251 | 0.0000 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ss_100C_1v60 | -0.5098 | -0.5098 | 0.0000 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ss_100C_1v60 | 30 | 30 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.1174 | -0.1174 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.1173 | 0.1173 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.1155 | -0.1155 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.1154 | 0.1154 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.1333 | -0.1333 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.1332 | 0.1332 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ss_100C_1v60 | -11.6629 | -11.6629 | 0.0000 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ss_100C_1v60 | -0.7305 | -0.7305 | 0.0000 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ss_100C_1v60 | 32 | 32 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.1202 | -0.1202 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.1201 | 0.1201 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/EF_UART
| Metric | Before | After | Delta |
|---|---|---|---|
| antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold | -0.1148 | -0.1148 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup | 0.1149 | 0.1149 | 0.0000 (0.0000%) ⭕ |
| design__core__area | 32371 | 32371 | 0 (0.0000%) ⭕ |
| design__die__area | 38786.2000 | 38786.2000 | 0.0000 (0.0000%) ⭕ |
| design__instance__area | 32371 | 32371 | 0 (0.0000%) ⭕ |
| design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count | 26 | 26 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| ir__drop__avg | 0.0003 | 0.0003 | 0.0000 (0.0000%) ⭕ |
| ir__drop__worst | 0.0009 | 0.0009 | 0.0000 (0.0000%) ⭕ |
| ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| power__internal__total | 0.0040 | 0.0040 | 0.0000 (0.0000%) ⭕ |
| power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
| power__switching__total | 0.0022 | 0.0022 | 0.0000 (0.0000%) ⭕ |
| power__total | 0.0061 | 0.0061 | 0.0000 (0.0000%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns | -12.4200 | -12.4200 | 0.0000 (0.0000%) ⭕ |
| timing__setup__wns | -1.2644 | -1.2644 | 0.0000 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count | 3 | 3 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count | 40 | 40 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.1215 | -0.1215 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.1217 | 0.1217 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 26 | 26 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.1428 | -0.1428 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.1429 | 0.1429 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 26 | 26 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ss_100C_1v60 | -12.4200 | -12.4200 | 0.0000 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ss_100C_1v60 | -1.2644 | -1.2644 | 0.0000 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 1 | 1 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ss_100C_1v60 | 14 | 14 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.1279 | -0.1279 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.1281 | 0.1281 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 26 | 26 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.1148 | -0.1148 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.1149 | 0.1149 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 26 | 26 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.1328 | -0.1328 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.1328 | 0.1328 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 26 | 26 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ss_100C_1v60 | -6.4656 | -6.4656 | 0.0000 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ss_100C_1v60 | -0.7435 | -0.7435 | 0.0000 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 1 | 1 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ss_100C_1v60 | 13 | 13 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.1197 | -0.1197 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.1198 | 0.1198 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 26 | 26 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.1174 | -0.1174 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.1175 | 0.1175 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 26 | 26 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.1370 | -0.1370 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.1370 | 0.1370 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 26 | 26 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ss_100C_1v60 | -9.3481 | -9.3481 | 0.0000 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ss_100C_1v60 | -1.0005 | -1.0005 | 0.0000 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 1 | 1 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ss_100C_1v60 | 13 | 13 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.1230 | -0.1230 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.1231 | 0.1231 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 26 | 26 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/MS_CLK_RST
| Metric | Before | After | Delta |
|---|---|---|---|
| antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold | -0.9025 | -0.9025 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup | -2.5383 | -2.5383 | 0.0000 (0.0000%) ⭕ |
| design__core__area | 9240.1100 | 9240.1100 | 0.0000 (0.0000%) ⭕ |
| design__die__area | 12909.2000 | 12909.2000 | 0.0000 (0.0000%) ⭕ |
| design__instance__area | 9240.1100 | 9240.1100 | 0.0000 (0.0000%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count | 2 | 2 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count | 4 | 4 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count | 133 | 133 | 0 (0.0000%) ⭕ |
| ir__drop__avg | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
| ir__drop__worst | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
| ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| power__internal__total | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
| power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
| power__switching__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
| power__total | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.9025 | -0.9025 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_ff_n40C_1v95 | -0.5961 | -0.5961 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 4 | 4 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_ss_100C_1v60 | -2.8432 | -2.8432 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_ss_100C_1v60 | -2.5383 | -2.5383 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 4 | 4 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ss_100C_1v60 | 133 | 133 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_tt_025C_1v80 | -1.5957 | -1.5957 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_tt_025C_1v80 | -1.2932 | -1.2932 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 4 | 4 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.9046 | -0.9046 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_ff_n40C_1v95 | -0.5984 | -0.5984 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 4 | 4 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_ss_100C_1v60 | -2.8252 | -2.8252 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_ss_100C_1v60 | -2.5202 | -2.5202 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 4 | 4 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ss_100C_1v60 | 133 | 133 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_tt_025C_1v80 | -1.5927 | -1.5927 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_tt_025C_1v80 | -1.2903 | -1.2903 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 4 | 4 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.9071 | -0.9071 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | -0.6008 | -0.6008 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 4 | 4 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -2.8374 | -2.8374 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_ss_100C_1v60 | -2.5325 | -2.5325 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 4 | 4 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 133 | 133 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -1.5980 | -1.5980 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_tt_025C_1v80 | -1.2955 | -1.2955 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 4 | 4 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/MS_DMAC_AHBL
| Metric | Before | After | Delta |
|---|---|---|---|
| timing__setup__tns | -77.7578 | -69.4640 | 8.2939 (-10.6663%) |
| timing__setup__wns | -1.5751 | -1.6489 | -0.0738 (+4.6858%) |
| timing__setup_vio__count | 223 | 230 | 7 (+3.1390%) |
| timing__setup__tns__corner:max_ss_100C_1v60 | -77.7578 | -69.4640 | 8.2939 (-10.6663%) |
| timing__setup__wns__corner:max_ss_100C_1v60 | -1.5751 | -1.6489 | -0.0738 (+4.6858%) |
| timing__setup_vio__count__corner:max_ss_100C_1v60 | 75 | 79 | 4 (+5.3333%) |
| timing__setup__tns__corner:min_ss_100C_1v60 | -54.5916 | -46.9339 | 7.6576 (-14.0271%) |
| timing__setup__wns__corner:min_ss_100C_1v60 | -1.2498 | -1.3158 | -0.0660 (+5.2808%) |
| timing__setup_vio__count__corner:min_ss_100C_1v60 | 74 | 75 | 1 (+1.3514%) |
| timing__setup__tns__corner:nom_ss_100C_1v60 | -65.7376 | -57.6924 | 8.0452 (-12.2384%) |
| timing__setup__wns__corner:nom_ss_100C_1v60 | -1.3669 | -1.4722 | -0.1054 (+7.7107%) |
| timing__setup_vio__count__corner:nom_ss_100C_1v60 | 74 | 76 | 2 (+2.7027%) |
| clock__skew__worst_hold | -0.2601 | -0.2569 | 0.0033 (-1.2543%) ❗ |
| clock__skew__worst_setup | 0.2608 | 0.2571 | -0.0037 (-1.4098%) ❗ |
| ir__drop__avg | 0.0005 | 0.0005 | 0.0000 (+1.0246%) ❗ |
| power__leakage__total | 0.0000 | 0.0000 | 0.0000 (+2.0649%) ❗ |
| clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.2652 | -0.2617 | 0.0035 (-1.3216%) ❗ |
| clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.2680 | 0.2629 | -0.0051 (-1.8904%) ❗ |
| clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.2774 | -0.2722 | 0.0052 (-1.8692%) ❗ |
| clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.2846 | 0.2724 | -0.0122 (-4.2983%) ❗ |
| clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.2685 | -0.2645 | 0.0039 (-1.4686%) ❗ |
| clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.2727 | 0.2663 | -0.0064 (-2.3471%) ❗ |
| design__max_slew_violation__count__corner:max_tt_025C_1v80 | 4 | 22 | 18 (+450.0000%) ❗ |
| clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.2601 | -0.2569 | 0.0033 (-1.2543%) ❗ |
| clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.2608 | 0.2571 | -0.0037 (-1.4098%) ❗ |
| clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.2691 | -0.2648 | 0.0044 (-1.6219%) ❗ |
| clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.2738 | 0.2648 | -0.0091 (-3.3206%) ❗ |
| clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.2628 | -0.2591 | 0.0037 (-1.4104%) ❗ |
| clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.2645 | 0.2597 | -0.0048 (-1.8156%) ❗ |
| design__max_slew_violation__count__corner:min_tt_025C_1v80 | 4 | 11 | 7 (+175.0000%) ❗ |
| clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.2615 | -0.2583 | 0.0032 (-1.2206%) ❗ |
| clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.2634 | 0.2589 | -0.0045 (-1.6959%) ❗ |
| clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.2729 | -0.2674 | 0.0055 (-2.0206%) ❗ |
| clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.2787 | 0.2674 | -0.0113 (-4.0651%) ❗ |
| clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.2644 | -0.2608 | 0.0036 (-1.3670%) ❗ |
| clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.2675 | 0.2617 | -0.0059 (-2.1898%) ❗ |
| design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 4 | 11 | 7 (+175.0000%) ❗ |
| design__core__area | 21688.3000 | 21620.7000 | -67.6000 (-0.3117%) ⭕ |
| design__die__area | 27029.9000 | 26821.4000 | -208.5000 (-0.7714%) ⭕ |
| design__instance__area | 21688.3000 | 21620.7000 | -67.6000 (-0.3117%) ⭕ |
| design__max_slew_violation__count | 269 | 266 | -3 (-1.1152%) ⭕ |
| ir__drop__worst | 0.0018 | 0.0016 | -0.0002 (-10.8571%) ⭕ |
| power__internal__total | 0.0022 | 0.0022 | -0.0000 (-0.3044%) ⭕ |
| power__switching__total | 0.0010 | 0.0010 | -0.0000 (-2.5559%) ⭕ |
| power__total | 0.0032 | 0.0032 | -0.0000 (-1.0350%) ⭕ |
| design__max_slew_violation__count__corner:max_ss_100C_1v60 | 269 | 266 | -3 (-1.1152%) ⭕ |
| design__max_slew_violation__count__corner:min_ss_100C_1v60 | 200 | 194 | -6 (-3.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 247 | 238 | -9 (-3.6437%) ⭕ |
| antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
| design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count | 1 | 1 | 0 (0.0000%) ⭕ |
| ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 1 | 1 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 1 | 1 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 1 | 1 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 1 | 1 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 1 | 1 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 1 | 1 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/MS_SPI_XIP_CACHE
| Metric | Before | After | Delta |
|---|---|---|---|
| antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold | -0.2656 | -0.2656 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup | 0.2718 | 0.2718 | 0.0000 (0.0000%) ⭕ |
| design__core__area | 124920 | 124920 | 0 (0.0000%) ⭕ |
| design__die__area | 136930 | 136930 | 0 (0.0000%) ⭕ |
| design__instance__area | 124920 | 124920 | 0 (0.0000%) ⭕ |
| design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count | 7 | 7 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count | 64 | 64 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count | 702 | 702 | 0 (0.0000%) ⭕ |
| ir__drop__avg | 0.0002 | 0.0002 | 0.0000 (0.0000%) ⭕ |
| ir__drop__worst | 0.0006 | 0.0006 | 0.0000 (0.0000%) ⭕ |
| ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| power__internal__total | 0.0086 | 0.0086 | 0.0000 (0.0000%) ⭕ |
| power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
| power__switching__total | 0.0031 | 0.0031 | 0.0000 (0.0000%) ⭕ |
| power__total | 0.0116 | 0.0116 | 0.0000 (0.0000%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns | -85.8153 | -85.8153 | 0.0000 (0.0000%) ⭕ |
| timing__setup__wns | -2.3047 | -2.3047 | 0.0000 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count | 46 | 46 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count | 199 | 199 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.2730 | -0.2730 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.2828 | 0.2828 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 64 | 64 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 45 | 45 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.2930 | -0.2930 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.3100 | 0.3100 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ss_100C_1v60 | 7 | 7 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 64 | 64 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ss_100C_1v60 | 702 | 702 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ss_100C_1v60 | -85.8153 | -85.8153 | 0.0000 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ss_100C_1v60 | -2.3047 | -2.3047 | 0.0000 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 26 | 26 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ss_100C_1v60 | 77 | 77 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.2783 | -0.2783 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.2907 | 0.2907 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_tt_025C_1v80 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 64 | 64 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_tt_025C_1v80 | 155 | 155 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.2656 | -0.2656 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.2718 | 0.2718 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 64 | 64 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 34 | 34 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.2842 | -0.2842 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.2963 | 0.2963 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ss_100C_1v60 | 3 | 3 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 64 | 64 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ss_100C_1v60 | 486 | 486 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ss_100C_1v60 | -47.7727 | -47.7727 | 0.0000 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ss_100C_1v60 | -1.6061 | -1.6061 | 0.0000 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 10 | 10 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ss_100C_1v60 | 61 | 61 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.2705 | -0.2705 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.2784 | 0.2784 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 64 | 64 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_tt_025C_1v80 | 82 | 82 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.2686 | -0.2686 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.2763 | 0.2763 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 64 | 64 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 34 | 34 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.2900 | -0.2900 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.3034 | 0.3034 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 4 | 4 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 64 | 64 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 565 | 565 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ss_100C_1v60 | -66.7707 | -66.7707 | 0.0000 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ss_100C_1v60 | -1.9782 | -1.9782 | 0.0000 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 10 | 10 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ss_100C_1v60 | 61 | 61 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.2740 | -0.2740 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.2833 | 0.2833 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 64 | 64 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 107 | 107 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/aes_upw_new
| Metric | Before | After | Delta |
|---|---|---|---|
| antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold | -3.2920 | -3.2920 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup | 0.2992 | 0.2992 | 0.0000 (0.0000%) ⭕ |
| design__core__area | 10174000 | 10174000 | 0 (0.0000%) ⭕ |
| design__die__area | 10278400 | 10278400 | 0 (0.0000%) ⭕ |
| design__instance__area | 656000 | 656000 | 0 (0.0000%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count | 987 | 987 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| ir__drop__avg | 0 | 0 | 0 (0.0000%) ⭕ |
| ir__drop__worst | 0 | 0 | 0 (0.0000%) ⭕ |
| ir__voltage__worst | 0 | 0 | 0 (0.0000%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| power__internal__total | 0.0159 | 0.0159 | 0.0000 (0.0000%) ⭕ |
| power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
| power__switching__total | 0.0151 | 0.0151 | 0.0000 (0.0000%) ⭕ |
| power__total | 0.0310 | 0.0310 | 0.0000 (0.0000%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -3.3127 | -3.3127 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.3206 | 0.3206 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 987 | 987 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_ss_100C_1v60 | -3.6492 | -3.6492 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.6638 | 0.6638 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 987 | 987 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_tt_025C_1v80 | -3.4170 | -3.4170 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.4268 | 0.4268 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 987 | 987 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -3.2920 | -3.2920 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.2992 | 0.2992 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 987 | 987 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_ss_100C_1v60 | -3.6017 | -3.6017 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.6147 | 0.6147 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 987 | 987 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_tt_025C_1v80 | -3.3863 | -3.3863 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.3956 | 0.3956 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 987 | 987 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -3.3007 | -3.3007 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.3085 | 0.3085 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 987 | 987 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -3.6238 | -3.6238 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.6379 | 0.6379 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 987 | 987 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -3.3998 | -3.3998 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.4097 | 0.4097 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 987 | 987 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/aes_upw_old
| Metric | Before | After | Delta |
|---|---|---|---|
| antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold | -3.2920 | -3.2920 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup | 0.2992 | 0.2992 | 0.0000 (0.0000%) ⭕ |
| design__core__area | 10174000 | 10174000 | 0 (0.0000%) ⭕ |
| design__die__area | 10278400 | 10278400 | 0 (0.0000%) ⭕ |
| design__instance__area | 656000 | 656000 | 0 (0.0000%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count | 987 | 987 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| ir__drop__avg | 0 | 0 | 0 (0.0000%) ⭕ |
| ir__drop__worst | 0 | 0 | 0 (0.0000%) ⭕ |
| ir__voltage__worst | 0 | 0 | 0 (0.0000%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| power__internal__total | 0.0159 | 0.0159 | 0.0000 (0.0000%) ⭕ |
| power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
| power__switching__total | 0.0151 | 0.0151 | 0.0000 (0.0000%) ⭕ |
| power__total | 0.0310 | 0.0310 | 0.0000 (0.0000%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -3.3127 | -3.3127 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.3206 | 0.3206 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 987 | 987 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_ss_100C_1v60 | -3.6492 | -3.6492 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.6638 | 0.6638 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 987 | 987 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_tt_025C_1v80 | -3.4170 | -3.4170 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.4268 | 0.4268 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 987 | 987 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -3.2920 | -3.2920 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.2992 | 0.2992 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 987 | 987 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_ss_100C_1v60 | -3.6017 | -3.6017 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.6147 | 0.6147 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 987 | 987 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_tt_025C_1v80 | -3.3863 | -3.3863 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.3956 | 0.3956 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 987 | 987 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -3.3007 | -3.3007 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.3085 | 0.3085 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 987 | 987 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -3.6238 | -3.6238 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.6379 | 0.6379 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 987 | 987 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -3.3998 | -3.3998 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.4097 | 0.4097 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 987 | 987 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/blink
| Metric | Before | After | Delta |
|---|---|---|---|
| design__max_slew_violation__count | 0 | 11 | 11 ❗ |
| design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 11 | 11 ❗ |
| design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 11 | 11 ❗ |
| clock__skew__worst_hold | -0.2514 | -0.2534 | -0.0020 (+0.7909%) ⭕ |
| clock__skew__worst_setup | 0.2514 | 0.2534 | 0.0020 (+0.7909%) ⭕ |
| design__core__area | 2477.3800 | 2409.8100 | -67.5700 (-2.7275%) ⭕ |
| design__die__area | 4483.0800 | 4336.5200 | -146.5600 (-3.2692%) ⭕ |
| design__instance__area | 2477.3800 | 2409.8100 | -67.5700 (-2.7275%) ⭕ |
| ir__drop__avg | 0.0001 | 0.0001 | -0.0000 (-3.4868%) ⭕ |
| ir__drop__worst | 0.0003 | 0.0002 | -0.0001 (-27.5093%) ⭕ |
| power__internal__total | 0.0002 | 0.0002 | -0.0000 (-0.0764%) ⭕ |
| power__leakage__total | 0.0000 | 0.0000 | -0.0000 (-7.8478%) ⭕ |
| power__switching__total | 0.0001 | 0.0000 | -0.0000 (-5.9819%) ⭕ |
| power__total | 0.0003 | 0.0003 | -0.0000 (-1.1838%) ⭕ |
| clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.2525 | -0.2543 | -0.0018 (+0.7013%) ⭕ |
| clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.2525 | 0.2543 | 0.0017 (+0.6897%) ⭕ |
| clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.2537 | -0.2584 | -0.0047 (+1.8414%) ⭕ |
| clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.2537 | 0.2584 | 0.0046 (+1.8310%) ⭕ |
| clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.2530 | -0.2559 | -0.0028 (+1.1161%) ⭕ |
| clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.2530 | 0.2558 | 0.0028 (+1.1048%) ⭕ |
| clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.2514 | -0.2534 | -0.0020 (+0.7909%) ⭕ |
| clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.2514 | 0.2534 | 0.0020 (+0.7909%) ⭕ |
| clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.2524 | -0.2567 | -0.0043 (+1.7019%) ⭕ |
| clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.2524 | 0.2567 | 0.0043 (+1.7019%) ⭕ |
| clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.2519 | -0.2547 | -0.0028 (+1.1237%) ⭕ |
| clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.2519 | 0.2547 | 0.0028 (+1.1237%) ⭕ |
| clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.2518 | -0.2539 | -0.0021 (+0.8356%) ⭕ |
| clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.2518 | 0.2539 | 0.0021 (+0.8355%) ⭕ |
| clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.2529 | -0.2577 | -0.0048 (+1.8882%) ⭕ |
| clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.2529 | 0.2577 | 0.0048 (+1.8882%) ⭕ |
| clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.2523 | -0.2553 | -0.0031 (+1.2200%) ⭕ |
| clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.2523 | 0.2553 | 0.0031 (+1.2200%) ⭕ |
| antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/caravel_upw
| Metric | Before | After | Delta |
|---|---|---|---|
| antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_setup | 0 | 0 | 0 (0.0000%) ⭕ |
| design__core__area | 10174000 | 10174000 | 0 (0.0000%) ⭕ |
| design__die__area | 10278400 | 10278400 | 0 (0.0000%) ⭕ |
| design__instance__area | 1080000 | 1080000 | 0 (0.0000%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count | 367 | 367 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count | 1101 | 1101 | 0 (0.0000%) ⭕ |
| ir__drop__avg | 0 | 0 | 0 (0.0000%) ⭕ |
| ir__drop__worst | 0 | 0 | 0 (0.0000%) ⭕ |
| ir__voltage__worst | 0 | 0 | 0 (0.0000%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| power__internal__total | 0 | 0 | 0 (0.0000%) ⭕ |
| power__leakage__total | 0 | 0 | 0 (0.0000%) ⭕ |
| power__switching__total | 0 | 0 | 0 (0.0000%) ⭕ |
| power__total | 0 | 0 | 0 (0.0000%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
| synthesis__check_error__count | 240 | 240 | 0 (0.0000%) ⭕ |
| timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 367 | 367 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 1101 | 1101 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ss_100C_1v60 | 367 | 367 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ss_100C_1v60 | 1101 | 1101 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_tt_025C_1v80 | 367 | 367 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_tt_025C_1v80 | 1101 | 1101 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 367 | 367 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 1101 | 1101 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ss_100C_1v60 | 367 | 367 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ss_100C_1v60 | 1101 | 1101 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_tt_025C_1v80 | 367 | 367 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_tt_025C_1v80 | 1101 | 1101 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 367 | 367 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 1101 | 1101 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 367 | 367 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 1101 | 1101 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 367 | 367 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 1101 | 1101 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/cell_inverter
| Metric | Before | After | Delta |
|---|---|---|---|
| design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/dual_spm
| Metric | Before | After | Delta |
|---|---|---|---|
| antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold | -0.2527 | -0.2527 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup | 0.2527 | 0.2527 | 0.0000 (0.0000%) ⭕ |
| design__core__area | 232536 | 232536 | 0 (0.0000%) ⭕ |
| design__die__area | 250000 | 250000 | 0 (0.0000%) ⭕ |
| design__instance__area | 212465 | 212465 | 0 (0.0000%) ⭕ |
| design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count | 38 | 38 | 0 (0.0000%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| power__internal__total | 0.0022 | 0.0022 | 0.0000 (0.0000%) ⭕ |
| power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
| power__switching__total | 0.0010 | 0.0010 | 0.0000 (0.0000%) ⭕ |
| power__total | 0.0032 | 0.0032 | 0.0000 (0.0000%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.2544 | -0.2544 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.2537 | 0.2537 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.2580 | -0.2580 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.2570 | 0.2570 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ss_100C_1v60 | 38 | 38 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.2557 | -0.2557 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.2549 | 0.2549 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.2527 | -0.2527 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.2527 | 0.2527 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.2556 | -0.2556 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.2553 | 0.2553 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.2537 | -0.2537 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.2537 | 0.2537 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.2532 | -0.2532 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.2532 | 0.2532 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.2564 | -0.2564 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.2561 | 0.2561 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.2544 | -0.2544 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.2543 | 0.2543 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/gcd
| Metric | Before | After | Delta |
|---|---|---|---|
| antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold | -0.2596 | -0.2596 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup | 0.2596 | 0.2596 | 0.0000 (0.0000%) ⭕ |
| design__core__area | 67039.3000 | 67039.3000 | 0.0000 (0.0000%) ⭕ |
| design__die__area | 78425.2000 | 78425.2000 | 0.0000 (0.0000%) ⭕ |
| design__instance__area | 67039.3000 | 67039.3000 | 0.0000 (0.0000%) ⭕ |
| design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count | 97 | 97 | 0 (0.0000%) ⭕ |
| ir__drop__avg | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
| ir__drop__worst | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
| ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| power__internal__total | 0.0005 | 0.0005 | 0.0000 (0.0000%) ⭕ |
| power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
| power__switching__total | 0.0005 | 0.0005 | 0.0000 (0.0000%) ⭕ |
| power__total | 0.0010 | 0.0010 | 0.0000 (0.0000%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.2618 | -0.2618 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.2618 | 0.2618 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.2730 | -0.2730 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.2730 | 0.2730 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ss_100C_1v60 | 97 | 97 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.2652 | -0.2652 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.2652 | 0.2652 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.2596 | -0.2596 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.2596 | 0.2596 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.2708 | -0.2708 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.2708 | 0.2708 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ss_100C_1v60 | 43 | 43 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.2627 | -0.2627 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.2627 | 0.2627 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.2609 | -0.2609 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.2609 | 0.2609 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.2721 | -0.2721 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.2721 | 0.2721 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 54 | 54 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.2641 | -0.2641 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.2641 | 0.2641 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/hold_violations_1
| Metric | Before | After | Delta |
|---|---|---|---|
| antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold | -0.2507 | -0.2507 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup | 0.2505 | 0.2505 | 0.0000 (0.0000%) ⭕ |
| design__core__area | 2190.8500 | 2190.8500 | 0.0000 (0.0000%) ⭕ |
| design__die__area | 4071.1100 | 4071.1100 | 0.0000 (0.0000%) ⭕ |
| design__instance__area | 2190.8500 | 2190.8500 | 0.0000 (0.0000%) ⭕ |
| design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| ir__drop__avg | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
| ir__drop__worst | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
| ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| power__internal__total | 0.0003 | 0.0003 | 0.0000 (0.0000%) ⭕ |
| power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
| power__switching__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
| power__total | 0.0003 | 0.0003 | 0.0000 (0.0000%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns | -1.4648 | -1.4648 | 0.0000 (0.0000%) ⭕ |
| timing__hold__wns | -0.0491 | -0.0491 | 0.0000 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count | 93 | 93 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count | 93 | 93 | 0 (0.0000%) ⭕ |
| timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.2511 | -0.2511 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.2512 | 0.2512 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ff_n40C_1v95 | -1.4386 | -1.4386 | 0.0000 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ff_n40C_1v95 | -0.0487 | -0.0487 | 0.0000 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 31 | 31 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ff_n40C_1v95 | 31 | 31 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.2517 | -0.2517 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.2515 | 0.2515 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.2512 | -0.2512 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.2513 | 0.2513 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.2507 | -0.2507 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.2505 | 0.2505 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ff_n40C_1v95 | -1.4648 | -1.4648 | 0.0000 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ff_n40C_1v95 | -0.0491 | -0.0491 | 0.0000 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 31 | 31 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ff_n40C_1v95 | 31 | 31 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.2513 | -0.2513 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.2510 | 0.2510 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.2509 | -0.2509 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.2506 | 0.2506 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.2508 | -0.2508 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.2507 | 0.2507 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ff_n40C_1v95 | -1.4531 | -1.4531 | 0.0000 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ff_n40C_1v95 | -0.0489 | -0.0489 | 0.0000 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 31 | 31 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 31 | 31 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.2515 | -0.2515 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.2511 | 0.2511 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.2510 | -0.2510 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.2508 | 0.2508 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/hold_violations_2
| Metric | Before | After | Delta |
|---|---|---|---|
| antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold | -0.2507 | -0.2507 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup | 0.2505 | 0.2505 | 0.0000 (0.0000%) ⭕ |
| design__core__area | 2190.8500 | 2190.8500 | 0.0000 (0.0000%) ⭕ |
| design__die__area | 4071.1100 | 4071.1100 | 0.0000 (0.0000%) ⭕ |
| design__instance__area | 2190.8500 | 2190.8500 | 0.0000 (0.0000%) ⭕ |
| design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| ir__drop__avg | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
| ir__drop__worst | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
| ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| power__internal__total | 0.0003 | 0.0003 | 0.0000 (0.0000%) ⭕ |
| power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
| power__switching__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
| power__total | 0.0003 | 0.0003 | 0.0000 (0.0000%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns | -1.9072 | -1.9072 | 0.0000 (0.0000%) ⭕ |
| timing__hold__wns | -0.7221 | -0.7221 | 0.0000 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count | 93 | 93 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count | 102 | 102 | 0 (0.0000%) ⭕ |
| timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.2511 | -0.2511 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.2512 | 0.2512 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ff_n40C_1v95 | -1.8848 | -1.8848 | 0.0000 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ff_n40C_1v95 | -0.4461 | -0.4461 | 0.0000 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 31 | 31 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ff_n40C_1v95 | 32 | 32 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.2517 | -0.2517 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.2515 | 0.2515 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ss_100C_1v60 | -0.7221 | -0.7221 | 0.0000 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ss_100C_1v60 | -0.7221 | -0.7221 | 0.0000 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ss_100C_1v60 | 1 | 1 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.2512 | -0.2512 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.2513 | 0.2513 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_tt_025C_1v80 | -0.5327 | -0.5327 | 0.0000 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_tt_025C_1v80 | -0.5327 | -0.5327 | 0.0000 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_tt_025C_1v80 | 1 | 1 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.2507 | -0.2507 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.2505 | 0.2505 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ff_n40C_1v95 | -1.9072 | -1.9072 | 0.0000 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ff_n40C_1v95 | -0.4422 | -0.4422 | 0.0000 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 31 | 31 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ff_n40C_1v95 | 32 | 32 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.2513 | -0.2513 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.2510 | 0.2510 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ss_100C_1v60 | -0.7129 | -0.7129 | 0.0000 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ss_100C_1v60 | -0.7129 | -0.7129 | 0.0000 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ss_100C_1v60 | 1 | 1 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.2509 | -0.2509 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.2506 | 0.2506 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_tt_025C_1v80 | -0.5269 | -0.5269 | 0.0000 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_tt_025C_1v80 | -0.5269 | -0.5269 | 0.0000 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_tt_025C_1v80 | 1 | 1 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.2508 | -0.2508 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.2507 | 0.2507 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ff_n40C_1v95 | -1.8973 | -1.8973 | 0.0000 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ff_n40C_1v95 | -0.4439 | -0.4439 | 0.0000 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 31 | 31 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 32 | 32 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.2515 | -0.2515 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.2511 | 0.2511 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ss_100C_1v60 | -0.7171 | -0.7171 | 0.0000 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ss_100C_1v60 | -0.7171 | -0.7171 | 0.0000 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ss_100C_1v60 | 1 | 1 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.2510 | -0.2510 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.2508 | 0.2508 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_tt_025C_1v80 | -0.5296 | -0.5296 | 0.0000 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_tt_025C_1v80 | -0.5296 | -0.5296 | 0.0000 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_tt_025C_1v80 | 1 | 1 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/hold_violations_3
| Metric | Before | After | Delta |
|---|---|---|---|
| antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold | -0.2500 | -0.2500 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup | 0.2500 | 0.2500 | 0.0000 (0.0000%) ⭕ |
| design__core__area | 16046.6000 | 16046.6000 | 0.0000 (0.0000%) ⭕ |
| design__die__area | 18225 | 18225 | 0 (0.0000%) ⭕ |
| design__instance__area | 14075.1000 | 14075.1000 | 0.0000 (0.0000%) ⭕ |
| design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| ir__drop__avg | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
| ir__drop__worst | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
| ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| power__internal__total | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
| power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
| power__switching__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
| power__total | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns | -0.0703 | -0.0703 | 0.0000 (0.0000%) ⭕ |
| timing__hold__wns | -0.0278 | -0.0278 | 0.0000 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count | 9 | 9 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count | 9 | 9 | 0 (0.0000%) ⭕ |
| timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.2503 | -0.2503 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.2504 | 0.2504 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ff_n40C_1v95 | -0.0544 | -0.0544 | 0.0000 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ff_n40C_1v95 | -0.0241 | -0.0241 | 0.0000 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 3 | 3 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ff_n40C_1v95 | 3 | 3 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.2508 | -0.2508 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.2509 | 0.2509 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.2504 | -0.2504 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.2506 | 0.2506 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.2500 | -0.2500 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.2500 | 0.2500 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ff_n40C_1v95 | -0.0703 | -0.0703 | 0.0000 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ff_n40C_1v95 | -0.0278 | -0.0278 | 0.0000 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 3 | 3 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ff_n40C_1v95 | 3 | 3 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.2501 | -0.2501 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.2501 | 0.2501 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.2500 | -0.2500 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.2501 | 0.2501 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.2500 | -0.2500 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.2501 | 0.2501 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ff_n40C_1v95 | -0.0626 | -0.0626 | 0.0000 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ff_n40C_1v95 | -0.0257 | -0.0257 | 0.0000 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 3 | 3 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 3 | 3 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.2502 | -0.2502 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.2503 | 0.2503 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.2501 | -0.2501 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.2502 | 0.2502 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/inverter
| Metric | Before | After | Delta |
|---|---|---|---|
| antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
| design__core__area | 1051.0100 | 1051.0100 | 0.0000 (0.0000%) ⭕ |
| design__die__area | 2500 | 2500 | 0 (0.0000%) ⭕ |
| design__instance__area | 1051.0100 | 1051.0100 | 0.0000 (0.0000%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/io_placer
| Metric | Before | After | Delta |
|---|---|---|---|
| antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_setup | 0 | 0 | 0 (0.0000%) ⭕ |
| design__core__area | 12273800 | 12273800 | 0 (0.0000%) ⭕ |
| design__die__area | 12390400 | 12390400 | 0 (0.0000%) ⭕ |
| design__instance__area | 1080000 | 1080000 | 0 (0.0000%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count | 367 | 367 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count | 1101 | 1101 | 0 (0.0000%) ⭕ |
| ir__drop__avg | 0 | 0 | 0 (0.0000%) ⭕ |
| ir__drop__worst | 0 | 0 | 0 (0.0000%) ⭕ |
| ir__voltage__worst | 0 | 0 | 0 (0.0000%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| power__internal__total | 0 | 0 | 0 (0.0000%) ⭕ |
| power__leakage__total | 0 | 0 | 0 (0.0000%) ⭕ |
| power__switching__total | 0 | 0 | 0 (0.0000%) ⭕ |
| power__total | 0 | 0 | 0 (0.0000%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
| synthesis__check_error__count | 240 | 240 | 0 (0.0000%) ⭕ |
| timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 367 | 367 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 1101 | 1101 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ss_100C_1v60 | 367 | 367 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ss_100C_1v60 | 1101 | 1101 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_tt_025C_1v80 | 367 | 367 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_tt_025C_1v80 | 1101 | 1101 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 367 | 367 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 1101 | 1101 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ss_100C_1v60 | 367 | 367 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ss_100C_1v60 | 1101 | 1101 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_tt_025C_1v80 | 367 | 367 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_tt_025C_1v80 | 1101 | 1101 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 367 | 367 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 1101 | 1101 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 367 | 367 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 1101 | 1101 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 367 | 367 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 1101 | 1101 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/latch_bad
| Metric | Before | After | Delta |
|---|---|---|---|
| design__instance__area | 15.0144 | 15.0144 | 0.0000 (0.0000%) ⭕ |
| design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/latch_good
| Metric | Before | After | Delta |
|---|---|---|---|
| design__instance__area | 15.0144 | 15.0144 | 0.0000 (0.0000%) ⭕ |
| design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/manual_macro_placement_test
| Metric | Before | After | Delta |
|---|---|---|---|
| antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold | 0.0357 | 0.0357 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup | 0.0136 | 0.0136 | 0.0000 (0.0000%) ⭕ |
| design__core__area | 80146.9000 | 80146.9000 | 0.0000 (0.0000%) ⭕ |
| design__die__area | 90000 | 90000 | 0 (0.0000%) ⭕ |
| design__instance__area | 71166.3000 | 71166.3000 | 0.0000 (0.0000%) ⭕ |
| design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count | 32 | 32 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| power__internal__total | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
| power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
| power__switching__total | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
| power__total | 0.0002 | 0.0002 | 0.0000 (0.0000%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_ff_n40C_1v95 | 0.0356 | 0.0356 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.0356 | 0.0356 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 32 | 32 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_ss_100C_1v60 | 0.0354 | 0.0354 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.0354 | 0.0354 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 32 | 32 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_tt_025C_1v80 | 0.0357 | 0.0357 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.0357 | 0.0357 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 32 | 32 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_ff_n40C_1v95 | 0.0143 | 0.0143 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.0143 | 0.0143 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 32 | 32 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_ss_100C_1v60 | 0.0136 | 0.0136 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.0136 | 0.0136 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 32 | 32 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_tt_025C_1v80 | 0.0140 | 0.0140 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.0140 | 0.0140 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 32 | 32 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | 0.0202 | 0.0202 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.0202 | 0.0202 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 32 | 32 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_ss_100C_1v60 | 0.0193 | 0.0193 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.0193 | 0.0193 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 32 | 32 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_tt_025C_1v80 | 0.0198 | 0.0198 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.0198 | 0.0198 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 32 | 32 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/non_const_async_reset
| Metric | Before | After | Delta |
|---|---|---|---|
| design__instance__area | 7.5072 | 7.5072 | 0.0000 (0.0000%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/partial_hierarchy
| Metric | Before | After | Delta |
|---|---|---|---|
| antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold | -0.2507 | -0.2507 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup | 0.2504 | 0.2504 | 0.0000 (0.0000%) ⭕ |
| design__core__area | 2148.3100 | 2148.3100 | 0.0000 (0.0000%) ⭕ |
| design__die__area | 3978.1600 | 3978.1600 | 0.0000 (0.0000%) ⭕ |
| design__instance__area | 2148.3100 | 2148.3100 | 0.0000 (0.0000%) ⭕ |
| design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| ir__drop__avg | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
| ir__drop__worst | 0.0002 | 0.0002 | 0.0000 (0.0000%) ⭕ |
| ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| power__internal__total | 0.0003 | 0.0003 | 0.0000 (0.0000%) ⭕ |
| power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
| power__switching__total | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
| power__total | 0.0003 | 0.0003 | 0.0000 (0.0000%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.2507 | -0.2507 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.2510 | 0.2510 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.2518 | -0.2518 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.2509 | 0.2509 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.2510 | -0.2510 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.2510 | 0.2510 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.2507 | -0.2507 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.2505 | 0.2505 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.2518 | -0.2518 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.2513 | 0.2513 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.2511 | -0.2511 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.2508 | 0.2508 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.2507 | -0.2507 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.2504 | 0.2504 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.2519 | -0.2519 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.2513 | 0.2513 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.2512 | -0.2512 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.2507 | 0.2507 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/regs_analog_ctrl_APB
| Metric | Before | After | Delta |
|---|---|---|---|
| antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold | -0.2887 | -0.2887 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup | 0.1000 | 0.1000 | 0.0000 (0.0000%) ⭕ |
| design__core__area | 147489 | 147489 | 0 (0.0000%) ⭕ |
| design__die__area | 168525 | 168525 | 0 (0.0000%) ⭕ |
| design__instance__area | 147489 | 147489 | 0 (0.0000%) ⭕ |
| design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count | 77 | 77 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count | 731 | 731 | 0 (0.0000%) ⭕ |
| ir__drop__avg | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
| ir__drop__worst | 0.0009 | 0.0009 | 0.0000 (0.0000%) ⭕ |
| ir__voltage__worst | 1.6000 | 1.6000 | 0.0000 (0.0000%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| power__internal__total | 0.0016 | 0.0016 | 0.0000 (0.0000%) ⭕ |
| power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
| power__switching__total | 0.0011 | 0.0011 | 0.0000 (0.0000%) ⭕ |
| power__total | 0.0027 | 0.0027 | 0.0000 (0.0000%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
| synthesis__check_error__count | 1 | 1 | 0 (0.0000%) ⭕ |
| timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns | -46.3315 | -46.3315 | 0.0000 (0.0000%) ⭕ |
| timing__setup__wns | -7.9954 | -7.9954 | 0.0000 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count | 31 | 31 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.3115 | -0.3115 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.1000 | 0.1000 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.6121 | -0.6121 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.1000 | 0.1000 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ss_100C_1v60 | 77 | 77 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ss_100C_1v60 | 731 | 731 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ss_100C_1v60 | -46.3315 | -46.3315 | 0.0000 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ss_100C_1v60 | -7.9954 | -7.9954 | 0.0000 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ss_100C_1v60 | 12 | 12 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.4011 | -0.4011 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.1000 | 0.1000 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.2887 | -0.2887 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.1000 | 0.1000 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.5641 | -0.5641 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.1000 | 0.1000 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ss_100C_1v60 | 47 | 47 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ss_100C_1v60 | 432 | 432 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ss_100C_1v60 | -32.4306 | -32.4306 | 0.0000 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ss_100C_1v60 | -6.5943 | -6.5943 | 0.0000 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ss_100C_1v60 | 8 | 8 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.3702 | -0.3702 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.1000 | 0.1000 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.3015 | -0.3015 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.1000 | 0.1000 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.5927 | -0.5927 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.1000 | 0.1000 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 70 | 70 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 673 | 673 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ss_100C_1v60 | -41.8278 | -41.8278 | 0.0000 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ss_100C_1v60 | -7.5349 | -7.5349 | 0.0000 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ss_100C_1v60 | 11 | 11 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.3879 | -0.3879 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.1000 | 0.1000 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/s44
| Metric | Before | After | Delta |
|---|---|---|---|
| antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold | -0.2510 | -0.2510 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup | 0.2513 | 0.2513 | 0.0000 (0.0000%) ⭕ |
| design__core__area | 33280.7000 | 33280.7000 | 0.0000 (0.0000%) ⭕ |
| design__die__area | 39709.7000 | 39709.7000 | 0.0000 (0.0000%) ⭕ |
| design__instance__area | 33280.7000 | 33280.7000 | 0.0000 (0.0000%) ⭕ |
| design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| ir__drop__avg | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
| ir__drop__worst | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
| ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| power__internal__total | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
| power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
| power__switching__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
| power__total | 0.0002 | 0.0002 | 0.0000 (0.0000%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.2513 | -0.2513 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.2518 | 0.2518 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.2525 | -0.2525 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.2530 | 0.2530 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.2517 | -0.2517 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.2522 | 0.2522 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.2510 | -0.2510 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.2513 | 0.2513 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.2521 | -0.2521 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.2524 | 0.2524 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.2514 | -0.2514 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.2517 | 0.2517 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.2511 | -0.2511 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.2515 | 0.2515 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.2524 | -0.2524 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.2529 | 0.2529 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.2516 | -0.2516 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.2520 | 0.2520 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/spm
| Metric | Before | After | Delta |
|---|---|---|---|
| antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold | -0.2512 | -0.2512 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup | 0.2511 | 0.2511 | 0.0000 (0.0000%) ⭕ |
| design__core__area | 8051.4700 | 8051.4700 | 0.0000 (0.0000%) ⭕ |
| design__die__area | 11317.8000 | 11317.8000 | 0.0000 (0.0000%) ⭕ |
| design__instance__area | 7544.7400 | 7544.7400 | 0.0000 (0.0000%) ⭕ |
| design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| ir__drop__avg | 0.0002 | 0.0002 | 0.0000 (0.0000%) ⭕ |
| ir__drop__worst | 0.0009 | 0.0009 | 0.0000 (0.0000%) ⭕ |
| ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| power__internal__total | 0.0010 | 0.0010 | 0.0000 (0.0000%) ⭕ |
| power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
| power__switching__total | 0.0005 | 0.0005 | 0.0000 (0.0000%) ⭕ |
| power__total | 0.0015 | 0.0015 | 0.0000 (0.0000%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.2517 | -0.2517 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.2512 | 0.2512 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.2527 | -0.2527 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.2525 | 0.2525 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.2520 | -0.2520 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.2518 | 0.2518 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.2512 | -0.2512 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.2511 | 0.2511 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.2523 | -0.2523 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.2522 | 0.2522 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.2516 | -0.2516 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.2515 | 0.2515 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.2514 | -0.2514 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.2512 | 0.2512 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.2526 | -0.2526 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.2525 | 0.2525 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.2518 | -0.2518 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.2517 | 0.2517 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/test_sram_macro
| Metric | Before | After | Delta |
|---|---|---|---|
| antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold | -0.5178 | -0.5178 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup | -0.4362 | -0.4362 | 0.0000 (0.0000%) ⭕ |
| design__core__area | 906252 | 906252 | 0 (0.0000%) ⭕ |
| design__die__area | 937500 | 937500 | 0 (0.0000%) ⭕ |
| design__instance__area | 867420 | 867420 | 0 (0.0000%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count | 3 | 3 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count | 70 | 70 | 0 (0.0000%) ⭕ |
| ir__drop__avg | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
| ir__drop__worst | 0.0004 | 0.0004 | 0.0000 (0.0000%) ⭕ |
| ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
| magic__drc_error__count | 532 | 532 | 0 (0.0000%) ⭕ |
| power__internal__total | 0.0018 | 0.0018 | 0.0000 (0.0000%) ⭕ |
| power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
| power__switching__total | 0.0003 | 0.0003 | 0.0000 (0.0000%) ⭕ |
| power__total | 0.0022 | 0.0022 | 0.0000 (0.0000%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.5599 | -0.5599 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.2500 | 0.2500 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 31 | 31 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.9362 | -0.9362 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_ss_100C_1v60 | -0.4362 | -0.4362 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ss_100C_1v60 | 3 | 3 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ss_100C_1v60 | 70 | 70 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.6898 | -0.6898 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.2500 | 0.2500 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_tt_025C_1v80 | 2 | 2 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_tt_025C_1v80 | 40 | 40 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.5178 | -0.5178 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.2500 | 0.2500 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 27 | 27 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.8669 | -0.8669 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_ss_100C_1v60 | -0.3669 | -0.3669 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ss_100C_1v60 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ss_100C_1v60 | 69 | 69 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.6333 | -0.6333 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.2500 | 0.2500 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_tt_025C_1v80 | 34 | 34 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.5394 | -0.5394 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.2500 | 0.2500 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 27 | 27 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.9052 | -0.9052 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_ss_100C_1v60 | -0.4052 | -0.4052 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 69 | 69 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.6615 | -0.6615 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.2500 | 0.2500 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 37 | 37 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/tt_um_urish_simon
| Metric | Before | After | Delta |
|---|---|---|---|
| antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold | -0.2586 | -0.2586 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup | 0.2580 | 0.2580 | 0.0000 (0.0000%) ⭕ |
| design__core__area | 16493.3000 | 16493.3000 | 0.0000 (0.0000%) ⭕ |
| design__die__area | 17954.7000 | 17954.7000 | 0.0000 (0.0000%) ⭕ |
| design__instance__area | 16493.3000 | 16493.3000 | 0.0000 (0.0000%) ⭕ |
| design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count | 247 | 247 | 0 (0.0000%) ⭕ |
| ir__drop__avg | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
| ir__drop__worst | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
| ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| power__internal__total | 0.0009 | 0.0009 | 0.0000 (0.0000%) ⭕ |
| power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
| power__switching__total | 0.0006 | 0.0006 | 0.0000 (0.0000%) ⭕ |
| power__total | 0.0015 | 0.0015 | 0.0000 (0.0000%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.2616 | -0.2616 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.2608 | 0.2608 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.2781 | -0.2781 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.2712 | 0.2712 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ss_100C_1v60 | 247 | 247 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.2673 | -0.2673 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.2643 | 0.2643 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.2586 | -0.2586 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.2580 | 0.2580 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.2721 | -0.2721 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.2663 | 0.2663 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ss_100C_1v60 | 170 | 170 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.2633 | -0.2633 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.2609 | 0.2609 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.2597 | -0.2597 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.2590 | 0.2590 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.2745 | -0.2745 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.2681 | 0.2681 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 192 | 192 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.2650 | -0.2650 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.2623 | 0.2623 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/usb
| Metric | Before | After | Delta |
|---|---|---|---|
| antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold | -0.2590 | -0.2590 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup | 0.2588 | 0.2588 | 0.0000 (0.0000%) ⭕ |
| design__core__area | 25109.1000 | 25109.1000 | 0.0000 (0.0000%) ⭕ |
| design__die__area | 30843.5000 | 30843.5000 | 0.0000 (0.0000%) ⭕ |
| design__instance__area | 25109.1000 | 25109.1000 | 0.0000 (0.0000%) ⭕ |
| design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count | 3 | 3 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| ir__drop__avg | 0.0006 | 0.0006 | 0.0000 (0.0000%) ⭕ |
| ir__drop__worst | 0.0016 | 0.0016 | 0.0000 (0.0000%) ⭕ |
| ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| power__internal__total | 0.0022 | 0.0022 | 0.0000 (0.0000%) ⭕ |
| power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
| power__switching__total | 0.0008 | 0.0008 | 0.0000 (0.0000%) ⭕ |
| power__total | 0.0031 | 0.0031 | 0.0000 (0.0000%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.2604 | -0.2604 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.2606 | 0.2606 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 3 | 3 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.2753 | -0.2753 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.2749 | 0.2749 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 3 | 3 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.2654 | -0.2654 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.2653 | 0.2653 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 3 | 3 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.2590 | -0.2590 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.2588 | 0.2588 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 3 | 3 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.2716 | -0.2716 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.2709 | 0.2709 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 3 | 3 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.2632 | -0.2632 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.2628 | 0.2628 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 3 | 3 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.2599 | -0.2599 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.2596 | 0.2596 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 3 | 3 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.2739 | -0.2739 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.2729 | 0.2729 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 3 | 3 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.2646 | -0.2646 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.2640 | 0.2640 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 3 | 3 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/usb_cdc_core
| Metric | Before | After | Delta |
|---|---|---|---|
| antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold | -0.2596 | -0.2596 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup | 0.2638 | 0.2638 | 0.0000 (0.0000%) ⭕ |
| design__core__area | 61825.5000 | 61825.5000 | 0.0000 (0.0000%) ⭕ |
| design__die__area | 70972.2000 | 70972.2000 | 0.0000 (0.0000%) ⭕ |
| design__instance__area | 61825.5000 | 61825.5000 | 0.0000 (0.0000%) ⭕ |
| design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count | 35 | 35 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count | 84 | 84 | 0 (0.0000%) ⭕ |
| ir__drop__avg | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
| ir__drop__worst | 0.0004 | 0.0004 | 0.0000 (0.0000%) ⭕ |
| ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| power__internal__total | 0.0017 | 0.0017 | 0.0000 (0.0000%) ⭕ |
| power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
| power__switching__total | 0.0007 | 0.0007 | 0.0000 (0.0000%) ⭕ |
| power__total | 0.0025 | 0.0025 | 0.0000 (0.0000%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.2614 | -0.2614 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.2638 | 0.2638 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 35 | 35 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.2763 | -0.2763 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.2841 | 0.2841 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 35 | 35 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ss_100C_1v60 | 84 | 84 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.2652 | -0.2652 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.2700 | 0.2700 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 35 | 35 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.2596 | -0.2596 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.2638 | 0.2638 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 35 | 35 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.2754 | -0.2754 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.2843 | 0.2843 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 35 | 35 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ss_100C_1v60 | 56 | 56 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.2641 | -0.2641 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.2694 | 0.2694 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 35 | 35 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.2601 | -0.2601 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.2641 | 0.2641 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 35 | 35 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.2761 | -0.2761 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.2845 | 0.2845 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 35 | 35 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 70 | 70 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.2650 | -0.2650 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.2700 | 0.2700 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 35 | 35 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/user_proj_timer
| Metric | Before | After | Delta |
|---|---|---|---|
| antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold | -0.2551 | -0.2551 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup | 0.2551 | 0.2551 | 0.0000 (0.0000%) ⭕ |
| design__core__area | 655604 | 655604 | 0 (0.0000%) ⭕ |
| design__die__area | 700000 | 700000 | 0 (0.0000%) ⭕ |
| design__instance__area | 655604 | 655604 | 0 (0.0000%) ⭕ |
| design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count | 2 | 2 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count | 45 | 45 | 0 (0.0000%) ⭕ |
| ir__drop__avg | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
| ir__drop__worst | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
| ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| power__internal__total | 0.0003 | 0.0003 | 0.0000 (0.0000%) ⭕ |
| power__leakage__total | 0.0000 | 0.0000 | 0.0000 (0.0000%) ⭕ |
| power__switching__total | 0.0001 | 0.0001 | 0.0000 (0.0000%) ⭕ |
| power__total | 0.0003 | 0.0003 | 0.0000 (0.0000%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.2566 | -0.2566 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.2565 | 0.2565 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 2 | 2 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.2615 | -0.2615 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.2615 | 0.2615 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ss_100C_1v60 | 45 | 45 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.2578 | -0.2578 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.2578 | 0.2578 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 2 | 2 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.2551 | -0.2551 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.2551 | 0.2551 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 2 | 2 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.2598 | -0.2598 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.2598 | 0.2598 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ss_100C_1v60 | 12 | 12 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.2561 | -0.2561 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.2561 | 0.2561 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 2 | 2 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.2557 | -0.2557 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.2557 | 0.2557 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 2 | 2 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.2606 | -0.2606 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.2606 | 0.2606 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 2 | 2 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 18 | 18 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.2569 | -0.2569 | 0.0000 (0.0000%) ⭕ |
| clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.2569 | 0.2569 | 0.0000 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 2 | 2 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/wbqspiflash
| Metric | Before | After | Delta |
|---|---|---|---|
| clock__skew__worst_hold | -0.2906 | -0.2723 | 0.0183 (-6.2827%) ❗ |
| clock__skew__worst_setup | 0.2944 | 0.2729 | -0.0215 (-7.2873%) ❗ |
| design__max_slew_violation__count | 178 | 197 | 19 (+10.6742%) ❗ |
| power__switching__total | 0.0003 | 0.0003 | 0.0000 (+0.8869%) ❗ |
| clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.2958 | -0.2843 | 0.0116 (-3.9047%) ❗ |
| clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.3026 | 0.2859 | -0.0167 (-5.5327%) ❗ |
| clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.3591 | -0.3098 | 0.0493 (-13.7374%) ❗ |
| clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.3754 | 0.3062 | -0.0692 (-18.4237%) ❗ |
| design__max_slew_violation__count__corner:max_ss_100C_1v60 | 178 | 197 | 19 (+10.6742%) ❗ |
| clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.3148 | -0.2873 | 0.0276 (-8.7623%) ❗ |
| clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.3245 | 0.2897 | -0.0348 (-10.7327%) ❗ |
| clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.2906 | -0.2723 | 0.0183 (-6.2827%) ❗ |
| clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.2944 | 0.2729 | -0.0215 (-7.2873%) ❗ |
| clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.3451 | -0.3004 | 0.0448 (-12.9707%) ❗ |
| clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.3577 | 0.2967 | -0.0610 (-17.0607%) ❗ |
| design__max_slew_violation__count__corner:min_ss_100C_1v60 | 72 | 92 | 20 (+27.7778%) ❗ |
| clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.3065 | -0.2791 | 0.0274 (-8.9351%) ❗ |
| clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.3129 | 0.2787 | -0.0342 (-10.9304%) ❗ |
| clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.2949 | -0.2756 | 0.0193 (-6.5493%) ❗ |
| clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.2990 | 0.2772 | -0.0218 (-7.3019%) ❗ |
| clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.3548 | -0.3049 | 0.0499 (-14.0550%) ❗ |
| clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.3679 | 0.3012 | -0.0668 (-18.1442%) ❗ |
| design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 109 | 151 | 42 (+38.5321%) ❗ |
| clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.3127 | -0.2819 | 0.0308 (-9.8371%) ❗ |
| clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.3194 | 0.2817 | -0.0377 (-11.8138%) ❗ |
| design__core__area | 73206.5000 | 72587.1000 | -619.4000 (-0.8461%) ⭕ |
| design__die__area | 83128.5000 | 81853.1000 | -1275.4000 (-1.5343%) ⭕ |
| design__instance__area | 73206.5000 | 72587.1000 | -619.4000 (-0.8461%) ⭕ |
| design__max_fanout_violation__count | 32 | 30 | -2 (-6.2500%) ⭕ |
| ir__drop__avg | 0.0000 | 0.0000 | -0.0000 (-1.6393%) ⭕ |
| ir__drop__worst | 0.0003 | 0.0003 | -0.0001 (-20.1780%) ⭕ |
| power__internal__total | 0.0010 | 0.0010 | -0.0000 (-1.7117%) ⭕ |
| power__leakage__total | 0.0000 | 0.0000 | -0.0000 (-2.3526%) ⭕ |
| power__total | 0.0013 | 0.0013 | -0.0000 (-1.0598%) ⭕ |
| design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 32 | 30 | -2 (-6.2500%) ⭕ |
| design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 32 | 30 | -2 (-6.2500%) ⭕ |
| design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 32 | 30 | -2 (-6.2500%) ⭕ |
| design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 32 | 30 | -2 (-6.2500%) ⭕ |
| design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 32 | 30 | -2 (-6.2500%) ⭕ |
| design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 32 | 30 | -2 (-6.2500%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 32 | 30 | -2 (-6.2500%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 32 | 30 | -2 (-6.2500%) ⭕ |
| design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 32 | 30 | -2 (-6.2500%) ⭕ |
| antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
| design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/xtea
| Metric | Before | After | Delta |
|---|---|---|---|
| ir__drop__avg | 0.0000 | 0.0000 | 0.0000 (+0.8097%) ❗ |
| power__internal__total | 0.0001 | 0.0001 | 0.0000 (+0.0661%) ❗ |
| power__switching__total | 0.0000 | 0.0000 | 0.0000 (+5.2035%) ❗ |
| power__total | 0.0002 | 0.0002 | 0.0000 (+0.9680%) ❗ |
| clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.2536 | -0.2522 | 0.0014 (-0.5498%) ❗ |
| clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.2543 | 0.2523 | -0.0019 (-0.7645%) ❗ |
| clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.2542 | -0.2538 | 0.0004 (-0.1457%) ❗ |
| clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.2556 | 0.2539 | -0.0017 (-0.6654%) ❗ |
| clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.2537 | -0.2527 | 0.0010 (-0.3855%) ❗ |
| clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.2546 | 0.2529 | -0.0018 (-0.6950%) ❗ |
| clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.2531 | 0.2530 | -0.0001 (-0.0374%) ❗ |
| clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.2522 | 0.2522 | -0.0000 (-0.0071%) ❗ |
| clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.2524 | 0.2520 | -0.0004 (-0.1686%) ❗ |
| clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.2539 | 0.2534 | -0.0005 (-0.1897%) ❗ |
| clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.2530 | 0.2525 | -0.0005 (-0.1817%) ❗ |
| clock__skew__worst_hold | -0.2513 | -0.2517 | -0.0004 (+0.1511%) ⭕ |
| clock__skew__worst_setup | 0.2517 | 0.2517 | 0.0000 (+0.0031%) ⭕ |
| ir__drop__worst | 0.0001 | 0.0001 | -0.0000 (-12.0000%) ⭕ |
| power__leakage__total | 0.0000 | 0.0000 | -0.0000 (-0.0764%) ⭕ |
| clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.2513 | -0.2517 | -0.0004 (+0.1511%) ⭕ |
| clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.2517 | 0.2517 | 0.0000 (+0.0031%) ⭕ |
| clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.2524 | -0.2531 | -0.0006 (+0.2537%) ⭕ |
| clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.2515 | -0.2521 | -0.0007 (+0.2633%) ⭕ |
| clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.2518 | -0.2519 | -0.0001 (+0.0525%) ⭕ |
| clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.2526 | -0.2535 | -0.0009 (+0.3413%) ⭕ |
| clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.2521 | -0.2524 | -0.0003 (+0.1363%) ⭕ |
| antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
| design__core__area | 80146.9000 | 80146.9000 | 0.0000 (0.0000%) ⭕ |
| design__die__area | 90000 | 90000 | 0 (0.0000%) ⭕ |
| design__instance__area | 80146.9000 | 80146.9000 | 0.0000 (0.0000%) ⭕ |
| design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hd/zipdiv
| Metric | Before | After | Delta |
|---|---|---|---|
| design__max_slew_violation__count | 34 | 77 | 43 (+126.4706%) ❗ |
| ir__drop__avg | 0.0001 | 0.0001 | 0.0000 (+1.3924%) ❗ |
| ir__drop__worst | 0.0003 | 0.0003 | 0.0001 (+19.7026%) ❗ |
| design__max_slew_violation__count__corner:max_ss_100C_1v60 | 34 | 77 | 43 (+126.4706%) ❗ |
| design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 34 | 45 | 11 (+32.3529%) ❗ |
| clock__skew__worst_hold | -0.2564 | -0.2571 | -0.0007 (+0.2739%) ⭕ |
| clock__skew__worst_setup | 0.2562 | 0.2569 | 0.0006 (+0.2390%) ⭕ |
| design__core__area | 31636.6000 | 30669.4000 | -967.2000 (-3.0572%) ⭕ |
| design__die__area | 38283.5000 | 37077.6000 | -1205.9000 (-3.1499%) ⭕ |
| design__instance__area | 31636.6000 | 30669.4000 | -967.2000 (-3.0572%) ⭕ |
| power__internal__total | 0.0010 | 0.0010 | -0.0000 (-0.7629%) ⭕ |
| power__leakage__total | 0.0000 | 0.0000 | -0.0000 (-4.3351%) ⭕ |
| power__switching__total | 0.0005 | 0.0005 | -0.0000 (-3.7244%) ⭕ |
| power__total | 0.0015 | 0.0014 | -0.0000 (-1.7492%) ⭕ |
| clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.2588 | -0.2610 | -0.0022 (+0.8406%) ⭕ |
| clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.2582 | 0.2598 | 0.0015 (+0.5938%) ⭕ |
| clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.2664 | -0.2706 | -0.0042 (+1.5620%) ⭕ |
| clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.2658 | 0.2694 | 0.0037 (+1.3830%) ⭕ |
| clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.2614 | -0.2643 | -0.0029 (+1.1260%) ⭕ |
| clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.2608 | 0.2631 | 0.0023 (+0.8882%) ⭕ |
| clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.2564 | -0.2571 | -0.0007 (+0.2739%) ⭕ |
| clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.2562 | 0.2569 | 0.0006 (+0.2390%) ⭕ |
| clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.2635 | -0.2646 | -0.0011 (+0.4108%) ⭕ |
| clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.2626 | 0.2644 | 0.0017 (+0.6556%) ⭕ |
| design__max_slew_violation__count__corner:min_ss_100C_1v60 | 21 | 7 | -14 (-66.6667%) ⭕ |
| clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.2588 | -0.2598 | -0.0010 (+0.3851%) ⭕ |
| clock__skew__worst_setup__corner:min_tt_025C_1v80 | 0.2586 | 0.2595 | 0.0009 (+0.3517%) ⭕ |
| clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -0.2573 | -0.2585 | -0.0011 (+0.4374%) ⭕ |
| clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 0.2571 | 0.2580 | 0.0009 (+0.3641%) ⭕ |
| clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -0.2647 | -0.2669 | -0.0022 (+0.8412%) ⭕ |
| clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 0.2641 | 0.2665 | 0.0024 (+0.9060%) ⭕ |
| clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -0.2599 | -0.2615 | -0.0016 (+0.6260%) ⭕ |
| clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 0.2596 | 0.2610 | 0.0014 (+0.5557%) ⭕ |
| antenna__violating__nets | 0 | 0 | 0 (0.0000%) ⭕ |
| antenna__violating__pins | 0 | 0 | 0 (0.0000%) ⭕ |
| design__lint_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__lvs_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count | 1 | 1 | 0 (0.0000%) ⭕ |
| ir__voltage__worst | 1.8000 | 1.8000 | 0.0000 (0.0000%) ⭕ |
| magic__drc_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| route__drc_errors | 0 | 0 | 0 (0.0000%) ⭕ |
| synthesis__check_error__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 1 | 1 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 1 | 1 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 1 | 1 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 1 | 1 | 0 (0.0000%) ⭕ |
| design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__tns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup__wns__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
| timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 | 0 | 0 (0.0000%) ⭕ |
sky130A/sky130_fd_sc_hdll/xtea
| Metric | Before | After | Delta |
|---|---|---|---|
| ir__drop__avg | 0.0000 | 0.0000 | 0.0000 (+22.5256%) ❗ |
| ir__drop__worst | 0.0001 | 0.0001 | 0.0000 (+44.6029%) ❗ |
| power__internal__total | 0.0001 | 0.0001 | 0.0000 (+0.0113%) ❗ |
| power__leakage__total | 0.0000 | 0.0000 | 0.0000 (+0.1212%) ❗ |
| clock__skew__worst_hold | -0.2522 | -0.2535 | -0.0013 (+0.4970%) ⭕ |
| clock__skew__worst_setup | 0.2518 | 0.2535 | 0.0016 (+0.6547%) ⭕ |
| power__switching__total | 0.0000 | 0.0000 | -0.0000 (-1.9957%) ⭕ |
| power__total | 0.0002 | 0.0002 | -0.0000 (-0.3583%) ⭕ |
| clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -0.2539 | -0.2560 | -0.0021 (+0.8406%) ⭕ |
| clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 0.2539 | 0.2560 | 0.0021 (+0.8221%) ⭕ |
| clock__skew__worst_hold__corner:max_ss_100C_1v60 | -0.2563 | -0.2593 | -0.0030 (+1.1642%) ⭕ |
| clock__skew__worst_setup__corner:max_ss_100C_1v60 | 0.2557 | 0.2593 | 0.0036 (+1.4048%) ⭕ |
| clock__skew__worst_hold__corner:max_tt_025C_1v80 | -0.2543 | -0.2569 | -0.0026 (+1.0385%) ⭕ |
| clock__skew__worst_setup__corner:max_tt_025C_1v80 | 0.2543 | 0.2569 | 0.0026 (+1.0211%) ⭕ |
| clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -0.2522 | -0.2535 | -0.0013 (+0.4970%) ⭕ |
| clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 0.2518 | 0.2535 | 0.0016 (+0.6547%) ⭕ |
| clock__skew__worst_hold__corner:min_ss_100C_1v60 | -0.2562 | -0.2567 | -0.0005 (+0.1853%) ⭕ |
| clock__skew__worst_setup__corner:min_ss_100C_1v60 | 0.2546 | 0.2567 | 0.0021 (+0.8230%) ⭕ |
| clock__skew__worst_hold__corner:min_tt_025C_1v80 | -0.2533 | -0.2544 | -0.0011 (+0.4323%) ⭕ |
| clock__skew__worst_setup__corner:min_tt_025C_1v80 |