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February 16, 2024 18:44
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HV3 ISA preliminary specification
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| HyRISC v3 ISA Specification: | |
| LI | |
| ADD | |
| ADDI | |
| SUB | |
| SUBI | |
| AND | |
| ANDI | |
| OR | |
| ORI | |
| XOR | |
| XORI | |
| SLT | |
| SLTI | |
| SLTU | |
| SLTIU | |
| EXTSB | |
| EXTSH | |
| LSL | |
| LSLI | |
| LSR | |
| LSRI | |
| ASR | |
| ASRI | |
| dst = RD | |
| src = RS + RT * IMM10 | |
| ..... R1, (R2, xalign(R3, 0x3FF)) | |
| ..... R1, (R2, xalign(0x7FFF)) | |
| LDL.B | |
| LDR.B | |
| LDR.H | |
| LDL.H | |
| LDR.W | |
| LDL.W | |
| LDR.D | |
| LDL.D | |
| STR.B | |
| STL.B | |
| STR.H | |
| STL.H | |
| STR.W | |
| STL.W | |
| STR.D | |
| STL.D | |
| LEAR.B | |
| LEAL.B | |
| LEAR.H | |
| LEAL.H | |
| LEAR.W | |
| LEAL.W | |
| LEAR.D | |
| LEAL.D | |
| LDRUH | |
| LDLUH | |
| LDRUW | |
| LDLUW | |
| LDRUD | |
| LDLUD | |
| STRUH | |
| STLUH | |
| STRUW | |
| STLUW | |
| STRUD | |
| STLUD | |
| /* | |
| +00000000: a | |
| +00000004: b | |
| +00000006: c | |
| 00 01 02 03 04 05 06 07 08 09 | |
| +00000000: aa aa aa aa bb bb cc cc cc cc | |
| */ | |
| struct __attribute__((packed)) { | |
| uint32_t a; | |
| uint16_t b; | |
| uint32_t c; // C is unaligned | |
| } unaligned_t; | |
| int main() { | |
| i32 a; | |
| struct unaligned_t u; | |
| u.c = 0xbaadf00d; | |
| } | |
| start: | |
| li t4, 0xbaadf00d | |
| stluw -6(fp), t4 | |
| stack: | |
| -0 -> a | |
| -4 -> u | |
| -4 -> u.a | |
| -8 -> u.b | |
| -10 -> u.c | |
| void hv3_load_halfword_unaligned(hv3_t* cpu, uint32_t* dst, uint32_t addr) { | |
| } | |
| LOAD.B R1, R2(R3, 0x3ff) | |
| LOAD.H | |
| LOAD.W | |
| STORE.B | |
| STORE.H | |
| STORE.W | |
| LEA.B | |
| LEA.H | |
| LEA.W | |
| Load/Store Unit: | |
| LSU: 1100xxxx xyyyyyzz zzziiiii iiiiiooo | |
| 000: LOAD.B | |
| 001: LOAD | |
| 010: LOAD | |
| 011: STORE | |
| 100: STORE | |
| 101: STORE | |
| 110: LEA | |
| 111: LEA | |
| LOAD.s R1,R2(R3,I) | |
| LOAD.s R1,R2(R3,I) | |
| ALU immediate: | |
| 000 ADDI | |
| 001 SUBI | |
| 010 ANDI | |
| 011 ORI | |
| 100 XORI | |
| 101 LI | |
| 110 SLTI | |
| 111 SLTIU | |
| ADDI R3, R4, 0x1ffff | |
| SLTIU R4, R4, 0x1ffff | |
| ALU register: | |
| ALUR: 0100xxxx xyyyyy-- ---zzzzz ----oooo | |
| 0000: ADD | |
| 0001: SUB | |
| 0010: AND | |
| 0011: OR | |
| 0100: XOR | |
| 0101: - | |
| 0110: SLT | |
| 0111: SLTU | |
| 1000: EXTSB | |
| 1001: EXTSH | |
| 1010: LSL | |
| 1011: LSR | |
| 1100: ASR | |
| 1101: LSLI | |
| 1110: LSRI | |
| 1111: ASRI | |
| 0000: ALUR | |
| 0001: BRR | |
| 0010: - | |
| 0011: COP | |
| 0100: CPX | |
| 0101: BRI | |
| 0110: - | |
| 0111: SYS | |
| 1000: ALUI | |
| 1001: ALUI | |
| 1010: ALUI | |
| 1011: ALUI | |
| 1100: LSU | |
| 1101: LSU | |
| 1110: LSU | |
| 1111: LSU | |
| a < b -> a < b | |
| a > b -> b < a | |
| a <= b -> !(b < a) | |
| a >= b -> !(a < b) | |
| a < b -> SLTU AT, R1, R2 | |
| a > b -> SLTU AT, R2, R1 | |
| a <= b -> SLTU AT, R2, R1 | |
| XORI AT, 1 | |
| a >= b -> SLTU AT, R1, R2 | |
| XORI AT, 1 | |
| a == b -> SUB AT, R1, R2 | |
| SLTIU AT, 1 | |
| a != b -> SUB AT, R1, R2 | |
| SLTU AT, R0, AT | |
| BLT R1, R2, I -> SLTU AT, R1, R2 | |
| BNE AT, R0, I | |
| BGT R1, R2, I -> SLTU AT, R2, R1 | |
| BNE AT, R0, I | |
| BLE R1, R2, I -> SLTU AT, R2, R1 | |
| BEQ AT, R0, I | |
| BGE R1, R2, I -> SLTU AT, R1, R2 | |
| BEQ AT, R0, I | |
| BEQ R1, R2, I -> BEQ R1, R2, I | |
| BNE R1, R2, I -> BNE R1, R2, I | |
| NOP -> ADD R0, R0, R0 | |
| MOV R1, R2 -> ADD R1, R0, R2 | |
| ADDI R1, R2, 0 | |
| NOT R1, R2 -> XORI R1, R2, -1 | |
| NEG R1, R2 -> SUB R1, R0, R2 | |
| INC R1, R2 -> ADDI R1, R2, 1 | |
| DEC R1, R2 -> ADDI R1, R2, -1 | |
| SUBI R1, R2, 1 | |
| EXTUB R1, R2 -> ANDI R1, R2, 0x1ff00 | |
| EXTUH R1, R2 -> ANDI R1, R2, 0x10000 | |
| 000: BEQ | |
| 001: BNE | |
| 010: - | |
| 011: - | |
| 100: - | |
| 101: - | |
| 110: - | |
| 111: - | |
| ALUI: 10soxxxx xyyyyyii iiiiiiii iiiiiioo | |
| ALUR: 0100xxxx xyyyyy-- ---zzzzz ----oooo | |
| 11ooxxxx xyyyyyzz zzziiiii iiiiiioo | |
| ---- Examples ---- | |
| int foo(int bar) { | |
| int c = 20; | |
| return bar * c; | |
| } | |
| int main(void) { | |
| int b = 10; | |
| int a = foo(b); | |
| return 0; | |
| } | |
| main: | |
| move fp, sp | |
| addi sp, -12 | |
| stl.w 8(sp), ra | |
| li t0, 10 | |
| stl.w 4(sp), t0 | |
| jal foo | |
| ldl.w a0, 4(sp) | |
| move a0, r0 | |
| ldl.w ra, 4(sp) | |
| jalr ra, r0 | |
| move sp, fp | |
| foo: | |
| move fp, sp | |
| addi sp, -8 | |
| stl.w 4(sp), ra | |
| li t0, 20 | |
| stl.w 0(sp), t0 | |
| ldl.w 0(sp), t0 | |
| muls? a0, t0, a0 | |
| ldl.w ra, 4(sp) | |
| jalr ra, r0 | |
| move sp, fp | |
| SP Data | |
| 7ffffffc main_ra | |
| 7ffffff8 b | |
| 7ffffff4 a | |
| 7ffffff0 foo_ra | |
| 7fffffec c | |
| ---- Coprocessors ---- | |
| COP0 is reserved to the System Control Unit (SCU) and is a mandatory | |
| coprocessor. | |
| Note: None of the following coprocessors are mandatory | |
| COP1 is reserved | |
| COP2 is reserved to the MMU (Memory Management Unit) | |
| COP3 is reserved to the CCU (Cache Control Unit) | |
| COP4 is reserved to the FPU (Floating Point Unit) | |
| COP5 is reserved to the VPU (Vector Processing Unit) | |
| COP6 and up are free to use | |
| COP0 - SCU | |
| COP1 - Reserved | |
| COP2 - MMU | |
| COP3 - CCU | |
| COP4 - FPU | |
| COP5 - VPU | |
| SCU registers: | |
| cop0r0 - CR0 Control Register 0 | |
| cop0r1 - RES Reserved (CR1) | |
| cop0r2 - PVR Processor Version Register | |
| cop0r3 - CPUID CPUID Register | |
| cop0r4 - FCR Feature Control Register | |
| cop0r5 - ECAUSE Exception Cause Register | |
| cop0r6 - EPC Exception Address Register | |
| cop0r7 - EVADDR Exception Vector Address | |
| CR0: RRRRRRRR RRRRRRRR RRRRRRRR RRRRRRmm | |
| R: Reserved | |
| m: Processor mode | |
| 00 - User | |
| 01 - System | |
| 10 - Kernel | |
| 11 - Hypervisor | |
| PVR: vvvvvvvv vvvvvvvv vvvvvvvv vvvvvvvv | |
| v: Processor Version | |
| 72337600: HV3 revision 0 | |
| IDR: 00000000 CCCCCCCC CCCCcccc cccccccc | |
| c: Core number | |
| C: Total core count | |
| 00001000 - Single core system (Core 0) | |
| 00008004 - 8-core system (Core 4) | |
| FCR: 00000000 00VFCMRS 00000000 00vfcmRs | |
| s: SCU present (hardwired to 1) S: SCU enabled (hardwired to 1) | |
| R: Reserved | |
| m: MMU present M: MMU enabled | |
| c: CCU present C: CCU enabled | |
| f: FPU present F: FPU enabled | |
| v: VPU present V: VPU enabled | |
| MMU registers: | |
| cop2r0 - MMUCTRL | |
| cop2r1 - | |
| ---- HV3 Machine Spec ---- | |
| HV3 reserves COP0 to the System Control Unit (SCU) | |
| HV3 core equipped with COP2 |
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