Created
August 17, 2023 15:59
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KT-R1 DTS of running kernel
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| /dts-v1/; | |
| / { | |
| model-part-name = "MT6789V/CD"; | |
| #size-cells = <0x02>; | |
| compatible = "mediatek,MT6789"; | |
| model-external-name = "MT6789V/CD"; | |
| #address-cells = <0x02>; | |
| interrupt-parent = <0x01>; | |
| model = "MT6789V/CD"; | |
| syscon@11210000 { | |
| compatible = "mediatek,mt6789-afe\0syscon"; | |
| reg = <0x00 0x11210000 0x00 0x1000>; | |
| phandle = <0x39>; | |
| #clock-cells = <0x01>; | |
| }; | |
| camisp_legacy@1a000000 { | |
| clock-names = "CAMSYS_CAM_CGPDN\0CAMSYS_CAMTG_CGPDN\0CAMSYS_CAMSV1_CGPDN\0CAMSYS_CAMSV2_CGPDN\0CAMSYS_CAMSV3_CGPDN\0CAMSYS_LARB13_CGPDN\0CAMSYS_LARB14_CGPDN\0CAMSYS_SENINF_CGPDN\0CAMSYS_MAIN_CAM2MM_GALS_CGPDN\0CAMSYS_RAWALARB16_CGPDN\0CAMSYS_RAWACAM_CGPDN\0CAMSYS_RAWATG_CGPDN\0CAMSYS_RAWBLARB17_CGPDN\0CAMSYS_RAWBCAM_CGPDN\0CAMSYS_RAWBTG_CGPDN\0TOPCKGEN_TOP_MUX_CAMTM"; | |
| mediatek,larb = <0x44>; | |
| compatible = "mediatek,camisp_legacy"; | |
| mediatek,platform = "mt6789"; | |
| dma-ranges = <0x02 0x00 0x02 0x00 0x01 0x00>; | |
| reg = <0x00 0x1a000000 0x00 0x10000>; | |
| clocks = <0x31 0x02 0x31 0x03 0x31 0x05 0x31 0x06 0x31 0x07 0x31 0x00 0x31 0x01 0x31 0x04 0x31 0x0a 0x30 0x00 0x30 0x01 0x30 0x02 0x2f 0x00 0x2f 0x01 0x2f 0x02 0x2a 0x2d>; | |
| phandle = <0xf9>; | |
| #clock-cells = <0x01>; | |
| power-domains = <0x2d 0x0c>; | |
| }; | |
| syscon@10000000 { | |
| compatible = "mediatek,mt6789-topckgen\0syscon"; | |
| reg = <0x00 0x10000000 0x00 0x1000>; | |
| phandle = <0x2a>; | |
| #clock-cells = <0x01>; | |
| }; | |
| camsv3_legacy@1a093000 { | |
| mediatek,larb = <0x44>; | |
| compatible = "mediatek,camsv3_legacy"; | |
| dma-ranges = <0x02 0x00 0x02 0x00 0x01 0x00>; | |
| reg = <0x00 0x1a093000 0x00 0x1000>; | |
| phandle = <0x101>; | |
| interrupts = <0x00 0x168 0x04 0x00>; | |
| }; | |
| pbm { | |
| compatible = "mediatek,pbm"; | |
| phandle = <0x10a>; | |
| }; | |
| thermal-ntc1 { | |
| io-channel-names = "sensor-channel"; | |
| compatible = "generic-adc-thermal"; | |
| #thermal-sensor-cells = <0x00>; | |
| io-channels = <0x18 0x00>; | |
| phandle = <0x1e>; | |
| temperature-lookup-table = <0xffff63c0 0x6e0 0xffff67a8 0x6dd 0xffff6b90 0x6da 0xffff6f78 0x6d7 0xffff7360 0x6d3 0xffff7748 0x6d0 0xffff7b30 0x6cc 0xffff7f18 0x6c8 0xffff8300 0x6c3 0xffff86e8 0x6bf 0xffff8ad0 0x6ba 0xffff8eb8 0x6b4 0xffff92a0 0x6af 0xffff9688 0x6a9 0xffff9a70 0x6a3 0xffff9e58 0x69d 0xffffa240 0x696 0xffffa628 0x68f 0xffffaa10 0x688 0xffffadf8 0x680 0xffffb1e0 0x678 0xffffb5c8 0x670 0xffffb9b0 0x667 0xffffbd98 0x65e 0xffffc180 0x654 0xffffc568 0x64a 0xffffc950 0x63f 0xffffcd38 0x634 0xffffd120 0x629 0xffffd508 0x61d 0xffffd8f0 0x611 0xffffdcd8 0x604 0xffffe0c0 0x5f7 0xffffe4a8 0x5ea 0xffffe890 0x5dc 0xffffec78 0x5cd 0xfffff060 0x5be 0xfffff448 0x5af 0xfffff830 0x59f 0xfffffc18 0x58f 0x00 0x57e 0x3e8 0x56d 0x7d0 0x55c 0xbb8 0x54a 0xfa0 0x537 0x1388 0x525 0x1770 0x512 0x1b58 0x4ff 0x1f40 0x4eb 0x2328 0x4d7 0x2710 0x4c3 0x2af8 0x4ae 0x2ee0 0x49a 0x32c8 0x485 0x36b0 0x470 0x3a98 0x45b 0x3e80 0x445 0x4268 0x430 0x4650 0x41a 0x4a38 0x405 0x4e20 0x3ef 0x5208 0x3da 0x55f0 0x3c4 0x59d8 0x3af 0x5dc0 0x399 0x61a8 0x384 0x6590 0x36f 0x6978 0x35a 0x6d60 0x345 0x7148 0x330 0x7530 0x31c 0x7918 0x307 0x7d00 0x2f3 0x80e8 0x2e0 0x84d0 0x2cc 0x88b8 0x2b9 0x8ca0 0x2a6 0x9088 0x293 0x9470 0x281 0x9858 0x26f 0x9c40 0x25d 0xa028 0x24c 0xa410 0x23b 0xa7f8 0x22b 0xabe0 0x21a 0xafc8 0x20b 0xb3b0 0x1fb 0xb798 0x1ec 0xbb80 0x1dd 0xbf68 0x1cf 0xc350 0x1c1 0xc738 0x1b3 0xcb20 0x1a6 0xcf08 0x199 0xd2f0 0x18c 0xd6d8 0x180 0xdac0 0x174 0xdea8 0x168 0xe290 0x15d 0xe678 0x152 0xea60 0x147 0xee48 0x13d 0xf230 0x133 0xf618 0x129 0xfa00 0x120 0xfde8 0x117 0x101d0 0x10e 0x105b8 0x105 0x109a0 0xfd 0x10d88 0xf5 0x11170 0xed 0x11558 0xe6 0x11940 0xde 0x11d28 0xd7 0x12110 0xd1 0x124f8 0xca 0x128e0 0xc4 0x12cc8 0xbd 0x130b0 0xb7 0x13498 0xb2 0x13880 0xac 0x13c68 0xa7 0x14050 0xa1 0x14438 0x9c 0x14820 0x97 0x14c08 0x93 0x14ff0 0x8e 0x153d8 0x8a 0x157c0 0x85 0x15ba8 0x81 0x15f90 0x7d 0x16378 0x79 0x16760 0x76 0x16b48 0x72 0x16f30 0x6f 0x17318 0x6b 0x17700 0x68 0x17ae8 0x65 0x17ed0 0x62 0x182b8 0x5f 0x186a0 0x5c 0x18a88 0x59 0x18e70 0x57 0x19258 0x54 0x19640 0x51 0x19a28 0x4f 0x19e10 0x4d 0x1a1f8 0x4a 0x1a5e0 0x48 0x1a9c8 0x46 0x1adb0 0x44 0x1b198 0x42 0x1b580 0x40 0x1b968 0x3e 0x1bd50 0x3d 0x1c138 0x3b 0x1c520 0x39 0x1c908 0x38 0x1ccf0 0x36 0x1d0d8 0x34 0x1d4c0 0x33 0x1d8a8 0x32 0x1dc90 0x30 0x1e078 0x2f 0x1e460 0x2e 0x1e848 0x2c>; | |
| }; | |
| pdchk { | |
| compatible = "mediatek,mt6789-pdchk"; | |
| }; | |
| syscon@1602f000 { | |
| compatible = "mediatek,mt6789-vdecsys\0syscon"; | |
| reg = <0x00 0x1602f000 0x00 0x1000>; | |
| phandle = <0x33>; | |
| #clock-cells = <0x01>; | |
| }; | |
| opp-table-ipe { | |
| compatible = "operating-points-v2"; | |
| phandle = <0x109>; | |
| opp-0 { | |
| opp-hz = <0x00 0xda64340>; | |
| opp-microvolt = <0x86470>; | |
| }; | |
| opp-1 { | |
| opp-hz = <0x00 0x1298be00>; | |
| opp-microvolt = <0x927c0>; | |
| }; | |
| opp-2 { | |
| opp-hz = <0x00 0x18cba800>; | |
| opp-microvolt = <0x9eb10>; | |
| }; | |
| opp-3 { | |
| opp-hz = <0x00 0x208b4c80>; | |
| opp-microvolt = <0xb1008>; | |
| }; | |
| }; | |
| syscon@11F01000 { | |
| compatible = "mediatek,mt6789-imp_iic_wrap_n\0syscon"; | |
| reg = <0x00 0x11f01000 0x00 0x1000>; | |
| phandle = <0x36>; | |
| #clock-cells = <0x01>; | |
| }; | |
| timer { | |
| compatible = "arm,armv8-timer"; | |
| interrupt-parent = <0x01>; | |
| phandle = <0xed>; | |
| clock-frequency = <0xc65d40>; | |
| interrupts = <0x01 0x0d 0x04 0x00 0x01 0x0e 0x04 0x00 0x01 0x0b 0x04 0x00 0x01 0x0a 0x04 0x00>; | |
| }; | |
| mdpm { | |
| compatible = "mediatek,mt6789-mdpm"; | |
| mediatek,md_generation = <0x1897>; | |
| phandle = <0x10b>; | |
| }; | |
| disable_unused { | |
| compatible = "simple-bus"; | |
| status = "okay"; | |
| phandle = <0xf3>; | |
| disable-unused-pd-venc { | |
| compatible = "mediatek,scpsys-disable-unused"; | |
| power-domains = <0x2d 0x09>; | |
| }; | |
| disable-unused-clk-topckgen { | |
| compatible = "mediatek,clk-disable-unused"; | |
| clocks = <0x2a 0x3f 0x2a 0x40 0x2a 0x41 0x2a 0x42 0x2a 0x43 0x2a 0x44 0x2a 0x45 0x2a 0x46 0x2a 0x47 0x2a 0x48 0x2a 0x49 0x2a 0x02 0x2a 0x04 0x2a 0x05 0x2a 0x06 0x2a 0x07 0x2a 0x08 0x2a 0x0b 0x2a 0x0c 0x2a 0x0d 0x2a 0x0e 0x2a 0x0f 0x2a 0x10 0x2a 0x11 0x2a 0x12 0x2a 0x13 0x2a 0x14 0x2a 0x15 0x2a 0x16 0x2a 0x17 0x2a 0x18 0x2a 0x19 0x2a 0x1b 0x2a 0x1c 0x2a 0x1d 0x2a 0x1e 0x2a 0x1f 0x2a 0x20 0x2a 0x21 0x2a 0x22 0x2a 0x24 0x2a 0x25 0x2a 0x26 0x2a 0x27 0x2a 0x28 0x2a 0x29 0x2a 0x2a 0x2a 0x2b 0x2a 0x2c 0x2a 0x2d 0x2a 0x2e 0x2a 0x2f 0x2a 0x32 0x2a 0x34 0x2a 0x35 0x2a 0x36 0x2a 0x37 0x2a 0x38 0x2a 0x39 0x2a 0x3a 0x2a 0x3b 0x2a 0x3c 0x2a 0x3d 0x2a 0x3e>; | |
| }; | |
| disable-unused-pd-disp { | |
| compatible = "mediatek,scpsys-disable-unused"; | |
| power-domains = <0x2d 0x0a>; | |
| }; | |
| disable-unused-pd-audio { | |
| compatible = "mediatek,scpsys-disable-unused"; | |
| power-domains = <0x2d 0x0b>; | |
| }; | |
| disable-unused-clk-imgsys1 { | |
| compatible = "mediatek,clk-disable-unused"; | |
| clocks = <0x34 0x00 0x34 0x01 0x34 0x02 0x34 0x03>; | |
| power-domains = <0x2d 0x06>; | |
| }; | |
| disable-unused-pd-cam { | |
| compatible = "mediatek,scpsys-disable-unused"; | |
| power-domains = <0x2d 0x0c>; | |
| }; | |
| disable-unused-pd-vdec { | |
| compatible = "mediatek,scpsys-disable-unused"; | |
| power-domains = <0x2d 0x08>; | |
| }; | |
| disable-unused-clk-imp_iic_wrap_en { | |
| compatible = "mediatek,clk-disable-unused"; | |
| clocks = <0x37 0x00 0x37 0x01 0x37 0x02 0x37 0x03>; | |
| }; | |
| disable-unused-clk-imp_iic_wrap_c { | |
| compatible = "mediatek,clk-disable-unused"; | |
| clocks = <0x3a 0x00 0x3a 0x01 0x3a 0x02>; | |
| }; | |
| disable-unused-pd-ipe { | |
| compatible = "mediatek,scpsys-disable-unused"; | |
| power-domains = <0x2d 0x07>; | |
| }; | |
| disable-unused-pd-cam_rawa { | |
| compatible = "mediatek,scpsys-disable-unused"; | |
| power-domains = <0x2d 0x0d>; | |
| }; | |
| disable-unused-clk-mmsys { | |
| compatible = "mediatek,clk-disable-unused"; | |
| clocks = <0x35 0x00 0x35 0x01 0x35 0x02 0x35 0x03 0x35 0x04 0x35 0x05 0x35 0x06 0x35 0x07 0x35 0x08 0x35 0x09 0x35 0x0a 0x35 0x0b 0x35 0x0c 0x35 0x0d 0x35 0x0e 0x35 0x0f 0x35 0x10 0x35 0x11 0x35 0x12 0x35 0x13 0x35 0x14 0x35 0x15 0x35 0x16>; | |
| power-domains = <0x2d 0x0a>; | |
| }; | |
| disable-unused-pd-cam_rawb { | |
| compatible = "mediatek,scpsys-disable-unused"; | |
| power-domains = <0x2d 0x0e>; | |
| }; | |
| disable-unused-clk-camsys_rawb { | |
| compatible = "mediatek,clk-disable-unused"; | |
| clocks = <0x2f 0x00 0x2f 0x01 0x2f 0x02>; | |
| power-domains = <0x2d 0x0e>; | |
| }; | |
| disable-unused-clk-vdecsys { | |
| compatible = "mediatek,clk-disable-unused"; | |
| clocks = <0x33 0x00 0x33 0x01 0x33 0x02 0x33 0x03 0x33 0x04 0x33 0x05 0x33 0x06 0x33 0x07>; | |
| power-domains = <0x2d 0x08>; | |
| }; | |
| disable-unused-clk-camsys_rawa { | |
| compatible = "mediatek,clk-disable-unused"; | |
| clocks = <0x30 0x00 0x30 0x01 0x30 0x02>; | |
| power-domains = <0x2d 0x0d>; | |
| }; | |
| disable-unused-clk-mdpsys { | |
| compatible = "mediatek,clk-disable-unused"; | |
| clocks = <0x2c 0x00 0x2c 0x01 0x2c 0x02 0x2c 0x03 0x2c 0x04 0x2c 0x05 0x2c 0x06 0x2c 0x07 0x2c 0x08 0x2c 0x09 0x2c 0x0a 0x2c 0x0b 0x2c 0x0c 0x2c 0x0d 0x2c 0x0e 0x2c 0x0f>; | |
| power-domains = <0x2d 0x0a>; | |
| }; | |
| disable-unused-clk-afe { | |
| compatible = "mediatek,clk-disable-unused"; | |
| clocks = <0x39 0x00 0x39 0x01 0x39 0x02 0x39 0x03 0x39 0x04 0x39 0x05 0x39 0x06 0x39 0x07 0x39 0x08 0x39 0x09 0x39 0x0a 0x39 0x0b 0x39 0x0c 0x39 0x0d 0x39 0x0e 0x39 0x0f 0x39 0x10 0x39 0x11 0x39 0x12 0x39 0x13 0x39 0x14>; | |
| power-domains = <0x2d 0x0b>; | |
| }; | |
| disable-unused-clk-ipesys { | |
| compatible = "mediatek,clk-disable-unused"; | |
| clocks = <0x2e 0x00 0x2e 0x01 0x2e 0x02 0x2e 0x03 0x2e 0x04 0x2e 0x05 0x2e 0x06 0x2e 0x07>; | |
| power-domains = <0x2d 0x07>; | |
| }; | |
| disable-unused-clk-imp_iic_wrap_w { | |
| compatible = "mediatek,clk-disable-unused"; | |
| clocks = <0x38 0x00 0x38 0x01>; | |
| }; | |
| disable-unused-clk-apmixedsys { | |
| compatible = "mediatek,clk-disable-unused"; | |
| clocks = <0x3b 0x00 0x3b 0x01 0x3b 0x02 0x3b 0x03 0x3b 0x04 0x3b 0x05 0x3b 0x06 0x3b 0x07 0x3b 0x08 0x3b 0x0a 0x3b 0x0b 0x3b 0x0c 0x3b 0x0d>; | |
| }; | |
| disable-unused-clk-camsys_main { | |
| compatible = "mediatek,clk-disable-unused"; | |
| clocks = <0x31 0x00 0x31 0x01 0x31 0x02 0x31 0x03 0x31 0x04 0x31 0x05 0x31 0x06 0x31 0x07 0x31 0x08 0x31 0x09 0x31 0x0a>; | |
| power-domains = <0x2d 0x0c>; | |
| }; | |
| disable-unused-clk-imp_iic_wrap_n { | |
| compatible = "mediatek,clk-disable-unused"; | |
| clocks = <0x36 0x00>; | |
| }; | |
| disable-unused-pd-isp { | |
| compatible = "mediatek,scpsys-disable-unused"; | |
| power-domains = <0x2d 0x06>; | |
| }; | |
| disable-unused-clk-vencsys { | |
| compatible = "mediatek,clk-disable-unused"; | |
| clocks = <0x32 0x00 0x32 0x01 0x32 0x02 0x32 0x03>; | |
| power-domains = <0x2d 0x09>; | |
| }; | |
| disable-unused-clk-infracfg_ao { | |
| compatible = "mediatek,clk-disable-unused"; | |
| clocks = <0x2b 0x00 0x2b 0x01 0x2b 0x02 0x2b 0x03 0x2b 0x04 0x2b 0x05 0x2b 0x06 0x2b 0x07 0x2b 0x08 0x2b 0x09 0x2b 0x0a 0x2b 0x0b 0x2b 0x0c 0x2b 0x0d 0x2b 0x0e 0x2b 0x0f 0x2b 0x10 0x2b 0x11 0x2b 0x12 0x2b 0x13 0x2b 0x14 0x2b 0x15 0x2b 0x16 0x2b 0x17 0x2b 0x18 0x2b 0x19 0x2b 0x1a 0x2b 0x1b 0x2b 0x1c 0x2b 0x1d 0x2b 0x1e 0x2b 0x1f 0x2b 0x20 0x2b 0x21 0x2b 0x22 0x2b 0x23 0x2b 0x24 0x2b 0x25 0x2b 0x26 0x2b 0x27 0x2b 0x28 0x2b 0x29 0x2b 0x2a 0x2b 0x2b 0x2b 0x2c 0x2b 0x2d 0x2b 0x2f 0x2b 0x30 0x2b 0x31 0x2b 0x32 0x2b 0x33 0x2b 0x34 0x2b 0x35 0x2b 0x36 0x2b 0x37 0x2b 0x38 0x2b 0x39 0x2b 0x3a 0x2b 0x3b 0x2b 0x3c 0x2b 0x3d>; | |
| }; | |
| }; | |
| mrdump_ext_rst { | |
| mode = "IRQ"; | |
| compatible = "mediatek, mrdump_ext_rst-eint"; | |
| status = "okay"; | |
| interrupt-parent = <0x49>; | |
| phandle = <0xdd>; | |
| interrupts = <0x00 0x08>; | |
| }; | |
| mtk_composite_v4l2_1 { | |
| compatible = "mediatek,mtk_composite_v4l2_1"; | |
| phandle = <0x107>; | |
| port@0 { | |
| endpoint { | |
| remote-endpoint = <0x1ec>; | |
| phandle = <0x1ea>; | |
| }; | |
| }; | |
| port@1 { | |
| endpoint { | |
| remote-endpoint = <0x1ed>; | |
| phandle = <0x1eb>; | |
| }; | |
| }; | |
| }; | |
| opp-table-vdec { | |
| compatible = "operating-points-v2"; | |
| phandle = <0xa9>; | |
| opp-0 { | |
| opp-hz = <0x00 0xcfe6a80>; | |
| opp-microvolt = <0x86470>; | |
| }; | |
| opp-1 { | |
| opp-hz = <0x00 0x1298be00>; | |
| opp-microvolt = <0x927c0>; | |
| }; | |
| opp-2 { | |
| opp-hz = <0x00 0x18cba800>; | |
| opp-microvolt = <0x9eb10>; | |
| }; | |
| opp-3 { | |
| opp-hz = <0x00 0x208b4c80>; | |
| opp-microvolt = <0xb1008>; | |
| }; | |
| }; | |
| cpuhvfs@00114400 { | |
| clk-div = <0xa2a0 0xa2a4 0xa2e0>; | |
| compatible = "mediatek,cpufreq-hybrid"; | |
| proc2-supply = <0x3f>; | |
| nvmem-cell-names = "lkginfo"; | |
| nvmem-cells = <0x40>; | |
| proc3-supply = <0x3e>; | |
| tbl-off = <0x04 0x4c 0x94>; | |
| pll-con = <0x20c 0x21c 0x25c>; | |
| clk-div-base = <0x3d>; | |
| proc1-supply = <0x3e>; | |
| apmixedsys = <0x3c>; | |
| reg = <0x00 0x114400 0x00 0xc00 0x00 0x11bc00 0x00 0x1400 0x00 0x112800 0x00 0x1800 0x00 0x114f40 0x00 0xc0>; | |
| phandle = <0xf6>; | |
| cslog-range = <0x3d0 0xfa0>; | |
| mcucfg-ver = <0x00>; | |
| reg-names = "USRAM\0CSRAM\0ESRAM"; | |
| }; | |
| sspm@10400000 { | |
| sspm_res_ram_size = <0x110000>; | |
| compatible = "mediatek,sspm"; | |
| sspm_res_ram_start = <0x9fd60000>; | |
| reg = <0x00 0x10400000 0x00 0x30000 0x00 0x10440000 0x00 0x10000 0x00 0x10480000 0x00 0x80>; | |
| phandle = <0xda>; | |
| interrupt-names = "ipc"; | |
| reg-names = "sspm_base\0cfgreg\0mbox_share"; | |
| interrupts = <0x00 0x111 0x04 0x00>; | |
| }; | |
| camsys_rawc_legacy@1a08f000 { | |
| compatible = "mediatek,camsys_rawc_legacy"; | |
| reg = <0x00 0x1a08f000 0x00 0x1000>; | |
| phandle = <0xff>; | |
| #clock-cells = <0x01>; | |
| }; | |
| thermal-ntc2 { | |
| io-channel-names = "sensor-channel"; | |
| compatible = "generic-adc-thermal"; | |
| #thermal-sensor-cells = <0x00>; | |
| io-channels = <0x18 0x01>; | |
| phandle = <0x1f>; | |
| temperature-lookup-table = <0xffff63c0 0x6e0 0xffff67a8 0x6dd 0xffff6b90 0x6da 0xffff6f78 0x6d7 0xffff7360 0x6d3 0xffff7748 0x6d0 0xffff7b30 0x6cc 0xffff7f18 0x6c8 0xffff8300 0x6c3 0xffff86e8 0x6bf 0xffff8ad0 0x6ba 0xffff8eb8 0x6b4 0xffff92a0 0x6af 0xffff9688 0x6a9 0xffff9a70 0x6a3 0xffff9e58 0x69d 0xffffa240 0x696 0xffffa628 0x68f 0xffffaa10 0x688 0xffffadf8 0x680 0xffffb1e0 0x678 0xffffb5c8 0x670 0xffffb9b0 0x667 0xffffbd98 0x65e 0xffffc180 0x654 0xffffc568 0x64a 0xffffc950 0x63f 0xffffcd38 0x634 0xffffd120 0x629 0xffffd508 0x61d 0xffffd8f0 0x611 0xffffdcd8 0x604 0xffffe0c0 0x5f7 0xffffe4a8 0x5ea 0xffffe890 0x5dc 0xffffec78 0x5cd 0xfffff060 0x5be 0xfffff448 0x5af 0xfffff830 0x59f 0xfffffc18 0x58f 0x00 0x57e 0x3e8 0x56d 0x7d0 0x55c 0xbb8 0x54a 0xfa0 0x537 0x1388 0x525 0x1770 0x512 0x1b58 0x4ff 0x1f40 0x4eb 0x2328 0x4d7 0x2710 0x4c3 0x2af8 0x4ae 0x2ee0 0x49a 0x32c8 0x485 0x36b0 0x470 0x3a98 0x45b 0x3e80 0x445 0x4268 0x430 0x4650 0x41a 0x4a38 0x405 0x4e20 0x3ef 0x5208 0x3da 0x55f0 0x3c4 0x59d8 0x3af 0x5dc0 0x399 0x61a8 0x384 0x6590 0x36f 0x6978 0x35a 0x6d60 0x345 0x7148 0x330 0x7530 0x31c 0x7918 0x307 0x7d00 0x2f3 0x80e8 0x2e0 0x84d0 0x2cc 0x88b8 0x2b9 0x8ca0 0x2a6 0x9088 0x293 0x9470 0x281 0x9858 0x26f 0x9c40 0x25d 0xa028 0x24c 0xa410 0x23b 0xa7f8 0x22b 0xabe0 0x21a 0xafc8 0x20b 0xb3b0 0x1fb 0xb798 0x1ec 0xbb80 0x1dd 0xbf68 0x1cf 0xc350 0x1c1 0xc738 0x1b3 0xcb20 0x1a6 0xcf08 0x199 0xd2f0 0x18c 0xd6d8 0x180 0xdac0 0x174 0xdea8 0x168 0xe290 0x15d 0xe678 0x152 0xea60 0x147 0xee48 0x13d 0xf230 0x133 0xf618 0x129 0xfa00 0x120 0xfde8 0x117 0x101d0 0x10e 0x105b8 0x105 0x109a0 0xfd 0x10d88 0xf5 0x11170 0xed 0x11558 0xe6 0x11940 0xde 0x11d28 0xd7 0x12110 0xd1 0x124f8 0xca 0x128e0 0xc4 0x12cc8 0xbd 0x130b0 0xb7 0x13498 0xb2 0x13880 0xac 0x13c68 0xa7 0x14050 0xa1 0x14438 0x9c 0x14820 0x97 0x14c08 0x93 0x14ff0 0x8e 0x153d8 0x8a 0x157c0 0x85 0x15ba8 0x81 0x15f90 0x7d 0x16378 0x79 0x16760 0x76 0x16b48 0x72 0x16f30 0x6f 0x17318 0x6b 0x17700 0x68 0x17ae8 0x65 0x17ed0 0x62 0x182b8 0x5f 0x186a0 0x5c 0x18a88 0x59 0x18e70 0x57 0x19258 0x54 0x19640 0x51 0x19a28 0x4f 0x19e10 0x4d 0x1a1f8 0x4a 0x1a5e0 0x48 0x1a9c8 0x46 0x1adb0 0x44 0x1b198 0x42 0x1b580 0x40 0x1b968 0x3e 0x1bd50 0x3d 0x1c138 0x3b 0x1c520 0x39 0x1c908 0x38 0x1ccf0 0x36 0x1d0d8 0x34 0x1d4c0 0x33 0x1d8a8 0x32 0x1dc90 0x30 0x1e078 0x2f 0x1e460 0x2e 0x1e848 0x2c>; | |
| }; | |
| reserved-memory { | |
| #size-cells = <0x02>; | |
| ranges; | |
| #address-cells = <0x02>; | |
| phandle = <0xdb>; | |
| mblock-8-atf-log-reserved { | |
| no-map; | |
| compatible = "mediatek,atf-log-reserved"; | |
| reg = <0x00 0xbfc00000 0x00 0x200000>; | |
| }; | |
| mblock-9-aee_debug_kinfo { | |
| no-map; | |
| compatible = "mediatek,aee_debug_kinfo"; | |
| reg = <0x00 0x48080000 0x00 0x10000>; | |
| phandle = <0x1fd>; | |
| }; | |
| mblock-23-md_mem_usage { | |
| no-map; | |
| compatible = "mediatek,md_mem_usage"; | |
| reg = <0x00 0xde000000 0x00 0x1470000>; | |
| }; | |
| mblock-13-framebuffer { | |
| compatible = "mediatek,framebuffer"; | |
| reg = <0x00 0xfeac6000 0x00 0x1539000>; | |
| }; | |
| mblock-2-dramc-rk1 { | |
| no-map; | |
| compatible = "mediatek,dramc-rk1"; | |
| reg = <0x01 0xbffff000 0x00 0x1000>; | |
| }; | |
| mblock-25-md_mem_usage { | |
| no-map; | |
| compatible = "mediatek,md_mem_usage"; | |
| reg = <0x00 0xe0800000 0x00 0x2b10000>; | |
| }; | |
| mblock-30-consys_emi_reserved { | |
| no-map; | |
| compatible = "mediatek,consys_emi_reserved"; | |
| reg = <0x00 0x7e000000 0x00 0x500000>; | |
| }; | |
| mblock-17-tee-secmem { | |
| no-map; | |
| compatible = "mediatek,tee-secmem"; | |
| reg = <0x00 0x7ea00000 0x00 0x800000>; | |
| }; | |
| mblock-12-aee_lk { | |
| compatible = "mediatek,aee_lk"; | |
| reg = <0x00 0x50700000 0x00 0x800000>; | |
| }; | |
| mblock-20-SCP-reserved { | |
| no-map; | |
| compatible = "mediatek,SCP-reserved"; | |
| reg = <0x00 0xbf600000 0x00 0x600000>; | |
| }; | |
| mblock-16-MCUPM-reserved { | |
| no-map; | |
| compatible = "mediatek,MCUPM-reserved"; | |
| reg = <0x00 0x7feb0000 0x00 0x100000>; | |
| }; | |
| mblock-10-pstore { | |
| no-map; | |
| compatible = "mediatek,pstore"; | |
| reg = <0x00 0x48090000 0x00 0xe0000>; | |
| }; | |
| mblock-1-dramc-rk0 { | |
| no-map; | |
| compatible = "mediatek,dramc-rk0"; | |
| reg = <0x00 0xbffff000 0x00 0x1000>; | |
| }; | |
| mblock-3-emi_mbist_buf { | |
| no-map; | |
| compatible = "mediatek,emi_mbist_buf"; | |
| reg = <0x00 0x7ffff000 0x00 0x1000>; | |
| }; | |
| mblock-27-ap_md_nc_smem { | |
| no-map; | |
| compatible = "mediatek,ap_md_nc_smem"; | |
| reg = <0x00 0x8e000000 0x00 0xe00000>; | |
| }; | |
| mblock-28-ap_md_c_smem { | |
| no-map; | |
| compatible = "mediatek,ap_md_c_smem"; | |
| reg = <0x00 0x8c000000 0x00 0x16a0000>; | |
| }; | |
| mblock-5-unmap2 { | |
| no-map; | |
| compatible = "mediatek,unmap2"; | |
| reg = <0x00 0x7f400000 0x00 0x400000>; | |
| }; | |
| mblock-14-BL31-reserved { | |
| no-map; | |
| compatible = "mediatek,BL31-reserved"; | |
| reg = <0x00 0x48200000 0x00 0x200000>; | |
| }; | |
| mblock-29-sspm_ap-shared { | |
| no-map; | |
| compatible = "mediatek,sspm_ap-shared"; | |
| reg = <0x00 0x9fd60000 0x00 0x110000>; | |
| }; | |
| mblock-19-platform-debug_dfdmcu_dump { | |
| no-map; | |
| compatible = "mediatek,platform-debug_dfdmcu_dump"; | |
| reg = <0x00 0xfe000000 0x00 0x100000>; | |
| }; | |
| mblock-11-minirdump { | |
| no-map; | |
| compatible = "mediatek,minirdump"; | |
| reg = <0x00 0x48170000 0x00 0x10000>; | |
| }; | |
| mblock-6-gz-log { | |
| compatible = "mediatek,gz-log"; | |
| reg = <0x00 0x7f200000 0x00 0x41000>; | |
| }; | |
| mblock-22-ccci_tag_mem { | |
| no-map; | |
| compatible = "mediatek,ccci_tag_mem"; | |
| reg = <0x00 0xbffef000 0x00 0x10000>; | |
| }; | |
| mblock-24-md_mem_usage { | |
| no-map; | |
| compatible = "mediatek,md_mem_usage"; | |
| reg = <0x00 0xdfc00000 0x00 0x430000>; | |
| }; | |
| mblock-4-gz { | |
| no-map; | |
| compatible = "mediatek,gz"; | |
| reg = <0x00 0x7f800000 0x00 0x600000>; | |
| }; | |
| mblock-7-log_store { | |
| compatible = "mediatek,log_store"; | |
| reg = <0x00 0x7ffbf000 0x00 0x40000>; | |
| }; | |
| mblock-26-md_mem_usage { | |
| no-map; | |
| compatible = "mediatek,md_mem_usage"; | |
| reg = <0x00 0xe5200000 0x00 0xe00000>; | |
| }; | |
| mblock-31-shared-dma-pool_wifi-reserve-memory_dma { | |
| no-map; | |
| compatible = "shared-dma-pool"; | |
| reg = <0x00 0xbf000000 0x00 0x600000>; | |
| phandle = <0x1fe>; | |
| }; | |
| ssmr-reserved-cma_memory { | |
| compatible = "shared-dma-pool"; | |
| alignment = <0x00 0x1000000>; | |
| reusable; | |
| phandle = <0x17>; | |
| size = <0x00 0xa000000>; | |
| }; | |
| mblock-15-SSPM-reserved { | |
| no-map; | |
| compatible = "mediatek,SSPM-reserved"; | |
| reg = <0x00 0x9fe70000 0x00 0x180000>; | |
| }; | |
| mblock-21-reserve-memory-scp_share { | |
| no-map; | |
| compatible = "mediatek,reserve-memory-scp_share"; | |
| reg = <0x00 0x8f000000 0x00 0x7a0000>; | |
| }; | |
| mblock-18-crypto_hw { | |
| no-map; | |
| compatible = "mediatek,crypto_hw"; | |
| reg = <0x00 0x48401000 0x00 0x1000>; | |
| }; | |
| }; | |
| syscon@17000000 { | |
| compatible = "mediatek,mt6789-vencsys\0syscon"; | |
| reg = <0x00 0x17000000 0x00 0x1000>; | |
| phandle = <0x32>; | |
| #clock-cells = <0x01>; | |
| }; | |
| mtk_ssc { | |
| ssc_disable = <0x01>; | |
| compatible = "mediatek,ssc"; | |
| phandle = <0x1ae>; | |
| safe-vlogic-uv = <0x927c0>; | |
| }; | |
| bp_thl { | |
| soc_limit = <0x0f>; | |
| compatible = "mediatek,mtk-bp-thl"; | |
| phandle = <0x10e>; | |
| soc_limit_ext = <0x14>; | |
| soc_limit_ext_release = <0x19>; | |
| }; | |
| cam_qos_legacy { | |
| l16_cam_rawi_r2_a = <0x20206>; | |
| l17_cam_ufdi_r2_b = <0x20225>; | |
| l16_cam_rsso_r1_a = <0x2020e>; | |
| l17_cam_ltmso_r1_b = <0x2022d>; | |
| l17_cam_rawi_r2_b = <0x20226>; | |
| l16_cam_cqi_r1_a = <0x20202>; | |
| operating-points-v2 = <0x41>; | |
| l17_cam_crzo_r1_b = <0x2022c>; | |
| l16_cam_ufdi_r2_a = <0x20205>; | |
| l13_cam_mrawo0 = <0x201a1>; | |
| l16_cam_rrzo_r1_a = <0x20201>; | |
| l17_cam_aaho_r1_b = <0x2022f>; | |
| l17_cam_rrzo_r1_b = <0x20221>; | |
| l16_cam_imgo_r1_a = <0x20200>; | |
| l17_cam_lsci_r1_b = <0x20230>; | |
| l17_cam_flko_r1_b = <0x2022a>; | |
| compatible = "mediatek,cam_qos_legacy"; | |
| l16_cam_lceso_r1_a = <0x2020b>; | |
| l16_cam_crzo_r1_a = <0x2020c>; | |
| l17_cam_yuvo_r1_b = <0x20224>; | |
| l17_cam_aao_r1_b = <0x20228>; | |
| l17_cam_rsso_r1_b = <0x2022e>; | |
| l13_cam_mrawi = <0x201a0>; | |
| l16_cam_aaho_r1_a = <0x2020f>; | |
| l16_cam_bpci_r1_a = <0x20203>; | |
| l17_cam_cqi_r1_b = <0x20222>; | |
| l13_cam_camsv4 = <0x201a6>; | |
| l17_cam_lceso_r1_b = <0x2022b>; | |
| dvfsrc-vcore-supply = <0x42>; | |
| l17_cam_afo_r1_b = <0x20229>; | |
| l13_cam_camsv6 = <0x201a8>; | |
| l13_cam_mrawo1 = <0x201a2>; | |
| l16_cam_afo_r1_a = <0x20209>; | |
| l16_cam_lsci_r1_a = <0x20210>; | |
| l17_cam_bpci_r1_b = <0x20223>; | |
| l16_cam_rawi_r3_a = <0x20207>; | |
| l17_cam_imgo_r1_b = <0x20220>; | |
| l16_cam_ltmso_r1_a = <0x2020d>; | |
| l16_cam_aao_r1_a = <0x20208>; | |
| l16_cam_flko_r1_a = <0x2020a>; | |
| l17_cam_rawi_r3_b = <0x20227>; | |
| l13_cam_camsv5 = <0x201a7>; | |
| l16_cam_yuvo_r1_a = <0x20204>; | |
| }; | |
| syscon@11EB4000 { | |
| compatible = "mediatek,mt6789-imp_iic_wrap_en\0syscon"; | |
| reg = <0x00 0x11eb4000 0x00 0x1000>; | |
| phandle = <0x37>; | |
| #clock-cells = <0x01>; | |
| }; | |
| subpmic_pmu_eint { | |
| status = "okay"; | |
| interrupt-parent = <0x49>; | |
| phandle = <0x1ad>; | |
| interrupts = <0x04 0x08>; | |
| }; | |
| touch { | |
| compatible = "mediatek,touch"; | |
| status = "okay"; | |
| interrupt-parent = <0x49>; | |
| phandle = <0xf7>; | |
| interrupts = <0x09 0x02>; | |
| }; | |
| fhctl@1000ce00 { | |
| compatible = "mediatek,mt6853-fhctl"; | |
| reg = <0x00 0x1000ce00 0x00 0x200 0x00 0x1000c000 0x00 0xe00>; | |
| phandle = <0x90>; | |
| map0 { | |
| domain = "top"; | |
| method = "fhctl-mcupm"; | |
| tvdpll { | |
| fh-id = <0x0e>; | |
| pll-id = <0x0a>; | |
| }; | |
| mfgpll { | |
| fh-id = <0x06>; | |
| pll-id = <0x09>; | |
| }; | |
| msdcpll { | |
| fh-id = <0x0b>; | |
| pll-id = <0x06>; | |
| }; | |
| npupll { | |
| fh-id = <0x04>; | |
| pll-id = <0x08>; | |
| }; | |
| mmpll { | |
| fh-id = <0x09>; | |
| pll-id = <0x07>; | |
| }; | |
| armpll_bl0 { | |
| fh-id = <0x01>; | |
| perms = <0x1c>; | |
| pll-id = <0x3e7>; | |
| }; | |
| mainpll { | |
| fh-id = <0x0a>; | |
| pll-id = <0x04>; | |
| }; | |
| armpll_ll { | |
| fh-id = <0x00>; | |
| perms = <0x1c>; | |
| pll-id = <0x3e7>; | |
| }; | |
| ccipll { | |
| fh-id = <0x05>; | |
| perms = <0x1c>; | |
| pll-id = <0x3e7>; | |
| }; | |
| armpll_bl1 { | |
| fh-id = <0x02>; | |
| perms = <0x1c>; | |
| pll-id = <0x3e7>; | |
| }; | |
| mpll { | |
| fh-id = <0x08>; | |
| perms = <0x1c>; | |
| pll-id = <0x3e7>; | |
| }; | |
| armpll_bl2 { | |
| fh-id = <0x03>; | |
| perms = <0x1c>; | |
| pll-id = <0x3e7>; | |
| }; | |
| }; | |
| }; | |
| mtk_ctd { | |
| bc12 = <0x53>; | |
| compatible = "mediatek,mtk_ctd"; | |
| bc12_sel = <0x00>; | |
| phandle = <0x62>; | |
| }; | |
| syscon@1a06f000 { | |
| compatible = "mediatek,mt6789-camsys_rawb\0syscon"; | |
| reg = <0x00 0x1a06f000 0x00 0x1000>; | |
| phandle = <0x2f>; | |
| #clock-cells = <0x01>; | |
| }; | |
| camera_af_hw_node { | |
| camaf_m1_pmic-supply = <0x164>; | |
| camaf_m2_pmic-supply = <0x194>; | |
| camaf_m3_pmic-supply = <0x194>; | |
| compatible = "mediatek,camera_af_lens"; | |
| status = "okay"; | |
| phandle = <0x108>; | |
| }; | |
| power-controller@10006000 { | |
| clock-names = "mfg\0isp\0ipe\0vdec\0venc\0mdp\0disp\0audio\0cam\0isp-0\0isp-1\0ipe-0\0ipe-1\0ipe-2\0ipe-3\0vdec-0\0vdec-1\0venc-0\0disp_lp-0\0disp-0\0disp-1\0disp-2\0disp-3\0audio-0\0audio-1\0cam-0\0cam-1\0cam_rawa-0\0cam_rawb-0"; | |
| compatible = "mediatek,mt6789-scpsys\0syscon"; | |
| #power-domain-cells = <0x01>; | |
| infracfg = <0x2b>; | |
| reg = <0x00 0x10006000 0x00 0x1000>; | |
| clocks = <0x2a 0x09 0x2a 0x06 0x2a 0x07 0x2a 0x2c 0x2a 0x2b 0x2a 0x05 0x2a 0x04 0x2a 0x17 0x2a 0x08 0x34 0x03 0x34 0x00 0x2e 0x02 0x2e 0x07 0x2e 0x00 0x2e 0x01 0x33 0x05 0x33 0x00 0x32 0x01 0x2c 0x04 0x35 0x0a 0x35 0x0f 0x35 0x13 0x35 0x14 0x2b 0x25 0x2b 0x20 0x31 0x00 0x31 0x01 0x30 0x00 0x2f 0x00>; | |
| phandle = <0x2d>; | |
| }; | |
| spmtwam@10006000 { | |
| spm_irq_sta = <0x128>; | |
| spm_twam_last_sta2 = <0x1d8>; | |
| spm_twam_last_sta0 = <0x1d0>; | |
| spm_twam_con = <0x990>; | |
| spm_twam_last_sta3 = <0x1dc>; | |
| compatible = "mediatek,spmtwam"; | |
| spm_twam_last_sta1 = <0x1d4>; | |
| reg = <0x00 0x10006000 0x00 0x1000>; | |
| spm_twam_idle_sel = <0x998>; | |
| phandle = <0x1a4>; | |
| spm_irq_mask = <0xb4>; | |
| interrupts = <0x00 0xfe 0x04 0x00>; | |
| spm_twam_window_len = <0x994>; | |
| }; | |
| ssmr { | |
| memory-region = <0x17>; | |
| compatible = "mediatek,trusted_mem"; | |
| }; | |
| aliases { | |
| i2c6 = "/soc/i2c@1101a000"; | |
| i2c4 = "/soc/i2c@11eb1000"; | |
| ccorr0 = "/soc/disp_ccorr0@1400b000"; | |
| i2c8 = "/soc/i2c@11eb2000"; | |
| dsc0 = "/soc/disp_dsc_wrap0@14012000"; | |
| ovl3 = "/soc/disp_ovl0_2l@14006000"; | |
| i2c2 = "/soc/i2c@11eb0000"; | |
| aal0 = "/soc/disp_aal0@1400c000"; | |
| i2c1 = "/soc/i2c@11e01000"; | |
| i2c7 = "/soc/i2c@11f00000"; | |
| wdma0 = "/soc/disp_wdma0@14014000"; | |
| rdma0 = "/soc/disp_rdma0@14007000"; | |
| i2c0 = "/soc/i2c@11e00000"; | |
| i2c9 = "/soc/i2c@11eb3000"; | |
| gamma0 = "/soc/disp_gamma0@1400d000"; | |
| i2c5 = "/soc/i2c@11017000"; | |
| ovl0 = "/soc/disp_ovl0@14005000"; | |
| dither0 = "/soc/disp_dither0@1400f000"; | |
| i2c3 = "/soc/i2c@11015000"; | |
| postmask0 = "/soc/disp_postmask0@1400e000"; | |
| dsi0 = "/soc/dsi@14013000"; | |
| color0 = "/soc/disp_color0@14009000"; | |
| }; | |
| md_attr_node { | |
| compatible = "mediatek,md_attr_node"; | |
| mediatek,md_drdi_rf_set_idx = <0xf0f0f0f>; | |
| mediatek,md_product_name_model_id = <0xf0f0f0f>; | |
| }; | |
| pe { | |
| ta_12v_support; | |
| vbat_threshold = <0x1036>; | |
| ta_start_battery_soc = <0x00>; | |
| pe_ichg_level_threshold = <0xf4240>; | |
| pe_charger_current = <0x2dc6c0>; | |
| gauge = <0xd3>; | |
| compatible = "mediatek,charger,pe"; | |
| ta_9v_support; | |
| min_charger_voltage = <0x4630c0>; | |
| ta_stop_battery_soc = <0x55>; | |
| ta_ac_9v_input_current = <0x30d400>; | |
| ta_ac_12v_input_current = <0x30d400>; | |
| phandle = <0x1a6>; | |
| ta_ac_7v_input_current = <0x30d400>; | |
| }; | |
| flashlight_core { | |
| compatible = "mediatek,flashlight_core"; | |
| phandle = <0x106>; | |
| }; | |
| backlight-cooler { | |
| compatible = "mediatek,backlight-cooler"; | |
| #cooling-cells = <0x02>; | |
| phandle = <0xe2>; | |
| backlight-names = "lcd-backlight"; | |
| }; | |
| cache-parity { | |
| compatible = "mediatek,mt6873-cache-parity"; | |
| ecc-irq-support = <0x01>; | |
| arm_dsu_ecc_hwirq = <0x20>; | |
| interrupts = <0x00 0x01 0x04 0x00 0x00 0x02 0x04 0x00 0x00 0x03 0x04 0x00 0x00 0x04 0x04 0x00 0x00 0x05 0x04 0x00 0x00 0x06 0x04 0x00 0x00 0x07 0x04 0x00 0x00 0x08 0x04 0x00 0x00 0x00 0x04 0x00>; | |
| }; | |
| debug-kinfo { | |
| memory-region = <0x1fd>; | |
| compatible = "google,debug-kinfo"; | |
| }; | |
| low_battery_throttling { | |
| hv_thd_volt = <0xd48>; | |
| compatible = "mediatek,low_battery_throttling"; | |
| lv1_thd_volt = <0xcb2>; | |
| lv2_thd_volt = <0xc1c>; | |
| }; | |
| clkchk { | |
| compatible = "mediatek,mt6789-clkchk"; | |
| }; | |
| rt-pd-manager { | |
| compatible = "mediatek,rt-pd-manager"; | |
| }; | |
| clkitg { | |
| compatible = "simple-bus"; | |
| status = "okay"; | |
| phandle = <0xf2>; | |
| bring-up { | |
| compatible = "mediatek,clk-bring-up"; | |
| clocks = <0x2a 0x18 0x2a 0x19 0x2a 0x2a 0x2b 0x00 0x2b 0x01 0x2b 0x04 0x2b 0x12 0x2b 0x19 0x2b 0x1a 0x2b 0x1e 0x2b 0x1f 0x2b 0x21 0x2b 0x24 0x2b 0x33 0x2b 0x34 0x2b 0x35 0x2b 0x38 0x2b 0x39 0x2b 0x3c>; | |
| }; | |
| }; | |
| mtk_lpm { | |
| logger-enable-states = "mcusysoff\0system_mem\0system_pll\0system_bus"; | |
| mcusys-cnt-chk = <0x01>; | |
| power-gs = <0x00>; | |
| #size-cells = <0x02>; | |
| compatible = "mediatek,mtk-lpm"; | |
| lpm-kernel-suspend = <0x00>; | |
| constraints = <0xca 0xcb 0xcc 0xcd>; | |
| ranges; | |
| #address-cells = <0x02>; | |
| resource-ctrl = <0xc5 0xc6 0xc7 0xc8 0xc9>; | |
| phandle = <0x1a0>; | |
| irq-remain = <0xc0 0xc1 0xc2 0xc3 0xc4>; | |
| suspend-method = "enable"; | |
| cg-shift = <0x00>; | |
| pll-shift = <0x10>; | |
| spm-cond = <0xce 0xcf>; | |
| irq-remain-list { | |
| level_usb { | |
| target = <0x64>; | |
| phandle = <0xc4>; | |
| value = <0x00 0x00 0x00 0x00>; | |
| }; | |
| level_btif_tx { | |
| target = <0xd2>; | |
| phandle = <0xc2>; | |
| value = <0x00 0x01 0x00 0x00>; | |
| }; | |
| edge_keypad { | |
| target = <0xd0>; | |
| phandle = <0xc0>; | |
| value = <0x01 0x00 0x00 0x04>; | |
| }; | |
| level_btif_rx { | |
| target = <0xd2>; | |
| phandle = <0xc3>; | |
| value = <0x00 0x02 0x00 0x00>; | |
| }; | |
| edge_mdwdt { | |
| target = <0xd1>; | |
| phandle = <0xc1>; | |
| value = <0x01 0x00 0x80000000 0x2000000>; | |
| }; | |
| }; | |
| spm-cond-list { | |
| spm_cond_cg { | |
| cg-name = "MTCMOS_0\0INFRA_0\0INFRA_1\0INFRA_2\0INFRA_3\0INFRA_4\0MMSYS_0\0MMSYS_3"; | |
| phandle = <0xce>; | |
| }; | |
| spm_cond_pll { | |
| pll-name = "UNIVPLL\0MFGPLL\0MSDCPLL\0TVPLL\0MMPLL"; | |
| phandle = <0xcf>; | |
| }; | |
| }; | |
| resource-ctrl-list { | |
| dram_s0 { | |
| id = <0x03>; | |
| phandle = <0xc8>; | |
| value = <0x00>; | |
| }; | |
| syspll { | |
| id = <0x02>; | |
| phandle = <0xc7>; | |
| value = <0x00>; | |
| }; | |
| dram_s1 { | |
| id = <0x04>; | |
| phandle = <0xc9>; | |
| value = <0x00>; | |
| }; | |
| bus26m { | |
| id = <0x00>; | |
| phandle = <0xc5>; | |
| value = <0x00>; | |
| }; | |
| infra { | |
| id = <0x01>; | |
| phandle = <0xc6>; | |
| value = <0x00>; | |
| }; | |
| }; | |
| lpm_sysram@0011b500 { | |
| compatible = "mediatek,lpm-sysram"; | |
| reg = <0x00 0x11b500 0x00 0x300>; | |
| phandle = <0x1a3>; | |
| }; | |
| power-gs-list { | |
| }; | |
| constraint-list { | |
| rc_bus26m { | |
| id = <0x00>; | |
| cond-info = <0x01>; | |
| phandle = <0xca>; | |
| value = <0x01>; | |
| rc-name = "bus26m"; | |
| }; | |
| rc_syspll { | |
| id = <0x01>; | |
| cond-info = <0x01>; | |
| phandle = <0xcb>; | |
| value = <0x01>; | |
| rc-name = "syspll"; | |
| }; | |
| rc_cpu_buck_ldo { | |
| id = <0x03>; | |
| cond-info = <0x00>; | |
| phandle = <0xcd>; | |
| value = <0x01>; | |
| rc-name = "cpu-buck-ldo"; | |
| }; | |
| rc_dram { | |
| id = <0x02>; | |
| cond-info = <0x01>; | |
| phandle = <0xcc>; | |
| value = <0x01>; | |
| rc-name = "dram"; | |
| }; | |
| }; | |
| cpupm-sysram@0011b000 { | |
| compatible = "mediatek,cpupm-sysram"; | |
| reg = <0x00 0x11b000 0x00 0x500>; | |
| phandle = <0x1a1>; | |
| }; | |
| mcusys-ctrl@0c53a000 { | |
| compatible = "mediatek,mcusys-ctrl"; | |
| reg = <0x00 0xc53a000 0x00 0x1000>; | |
| phandle = <0x1a2>; | |
| }; | |
| }; | |
| mcupm@0c540000 { | |
| compatible = "mediatek,mcupm"; | |
| reg = <0x00 0xc540000 0x00 0x22000 0x00 0xc55fb00 0x00 0xa0 0x00 0xc562004 0x00 0x04 0x00 0xc560074 0x00 0x04 0x00 0xc562000 0x00 0x04 0x00 0xc560078 0x00 0x04 0x00 0xc55fba0 0x00 0xa0 0x00 0xc562004 0x00 0x04 0x00 0xc560074 0x00 0x04 0x00 0xc562000 0x00 0x04 0x00 0xc560078 0x00 0x04 0x00 0xc55fc40 0x00 0xa0 0x00 0xc562004 0x00 0x04 0x00 0xc560074 0x00 0x04 0x00 0xc562000 0x00 0x04 0x00 0xc560078 0x00 0x04 0x00 0xc55fce0 0x00 0xa0 0x00 0xc562004 0x00 0x04 0x00 0xc560074 0x00 0x04 0x00 0xc562000 0x00 0x04 0x00 0xc560078 0x00 0x04 0x00 0xc55fd80 0x00 0xa0 0x00 0xc562004 0x00 0x04 0x00 0xc560074 0x00 0x04 0x00 0xc562000 0x00 0x04 0x00 0xc560078 0x00 0x04 0x00 0xc55fe20 0x00 0xa0 0x00 0xc562004 0x00 0x04 0x00 0xc560074 0x00 0x04 0x00 0xc562000 0x00 0x04 0x00 0xc560078 0x00 0x04 0x00 0xc55fec0 0x00 0xa0 0x00 0xc562004 0x00 0x04 0x00 0xc560074 0x00 0x04 0x00 0xc562000 0x00 0x04 0x00 0xc560078 0x00 0x04 0x00 0xc55ff60 0x00 0xa0 0x00 0xc562004 0x00 0x04 0x00 0xc560074 0x00 0x04 0x00 0xc562000 0x00 0x04 0x00 0xc560078 0x00 0x04>; | |
| phandle = <0xeb>; | |
| interrupt-names = "mbox0\0mbox1\0mbox2\0mbox3\0mbox4\0mbox5\0mbox6\0mbox7"; | |
| reg-names = "mcupm_base\0mbox0_base\0mbox0_set\0mbox0_clr\0mbox0_send\0mbox0_recv\0mbox1_base\0mbox1_set\0mbox1_clr\0mbox1_send\0mbox1_recv\0mbox2_base\0mbox2_set\0mbox2_clr\0mbox2_send\0mbox2_recv\0mbox3_base\0mbox3_set\0mbox3_clr\0mbox3_send\0mbox3_recv\0mbox4_base\0mbox4_set\0mbox4_clr\0mbox4_send\0mbox4_recv\0mbox5_base\0mbox5_set\0mbox5_clr\0mbox5_send\0mbox5_recv\0mbox6_base\0mbox6_set\0mbox6_clr\0mbox6_send\0mbox6_recv\0mbox7_base\0mbox7_set\0mbox7_clr\0mbox7_send\0mbox7_recv"; | |
| interrupts = <0x00 0x21 0x04 0x00 0x00 0x22 0x04 0x00 0x00 0x23 0x04 0x00 0x00 0x24 0x04 0x00 0x00 0x25 0x04 0x00 0x00 0x26 0x04 0x00 0x00 0x27 0x04 0x00 0x00 0x28 0x04 0x00>; | |
| }; | |
| opp-table-img { | |
| compatible = "operating-points-v2"; | |
| phandle = <0xb8>; | |
| opp-0 { | |
| opp-hz = <0x00 0xda64340>; | |
| opp-microvolt = <0x86470>; | |
| }; | |
| opp-1 { | |
| opp-hz = <0x00 0x1471c3c0>; | |
| opp-microvolt = <0x927c0>; | |
| }; | |
| opp-2 { | |
| opp-hz = <0x00 0x1b4c8680>; | |
| opp-microvolt = <0x9eb10>; | |
| }; | |
| opp-3 { | |
| opp-hz = <0x00 0x25317c00>; | |
| opp-microvolt = <0xb1008>; | |
| }; | |
| }; | |
| pe4 { | |
| pe40_r_cable_3a_lower = <0xf0>; | |
| low_temp_to_leave_pe40 = <0x0a>; | |
| dual_polling_ieoc = <0x6ddd0>; | |
| pe40_stop_battery_soc = <0x50>; | |
| vbat_threshold = <0x1036>; | |
| high_temp_to_leave_pe40 = <0x2e>; | |
| slave_mivr_diff = <0x186a0>; | |
| gauge = <0xd3>; | |
| compatible = "mediatek,charger,pe4"; | |
| ibus_err = <0x0e>; | |
| pe40_r_cable_1a_lower = <0x1f4>; | |
| min_charger_voltage = <0x4630c0>; | |
| high_temp_to_enter_pe40 = <0x27>; | |
| dcs_chg2_charger_current = <0x16e360>; | |
| dcs_input_current = <0x30d400>; | |
| sc_input_current = <0x30d400>; | |
| phandle = <0x1a9>; | |
| sc_charger_current = <0x2dc6c0>; | |
| dcs_chg1_charger_current = <0x16e360>; | |
| pe40_r_cable_2a_lower = <0x15f>; | |
| low_temp_to_enter_pe40 = <0x10>; | |
| }; | |
| syscon@1000C000 { | |
| compatible = "mediatek,mt6789-apmixedsys\0syscon"; | |
| reg = <0x00 0x1000c000 0x00 0x1000>; | |
| phandle = <0x3b>; | |
| #clock-cells = <0x01>; | |
| }; | |
| camsys_rawa_legacy@1a04f000 { | |
| compatible = "mediatek,camsys_rawa_legacy"; | |
| reg = <0x00 0x1a04f000 0x00 0x1000>; | |
| phandle = <0xfb>; | |
| #clock-cells = <0x01>; | |
| }; | |
| camsys_rawb_legacy@1a06f000 { | |
| compatible = "mediatek,camsys_rawb_legacy"; | |
| reg = <0x00 0x1a06f000 0x00 0x1000>; | |
| phandle = <0xfd>; | |
| #clock-cells = <0x01>; | |
| }; | |
| pd_adapter { | |
| phys = <0x63 0x03>; | |
| boot_mode = <0x50>; | |
| compatible = "mediatek,pd_adapter"; | |
| force_cv; | |
| phy-names = "usb2-phy"; | |
| phandle = <0x1ac>; | |
| adapter_name = "pd_adapter"; | |
| }; | |
| bootprof { | |
| logo_t = <0x4b8>; | |
| tfa_t = <0x18>; | |
| sec_os_t = <0x00>; | |
| bl2_ext_t = <0x519>; | |
| lk_t = <0x6c2>; | |
| pl_t = <0x62e>; | |
| gz_t = <0x00>; | |
| }; | |
| cam3_legacy@1a070000 { | |
| compatible = "mediatek,cam3_legacy"; | |
| reg = <0x00 0x1a070000 0x00 0x8000>; | |
| phandle = <0xfe>; | |
| }; | |
| cm_mgr@0c530000 { | |
| cm_mgr,vp_up = <0x64 0x64 0x64 0x64 0x64 0x64>; | |
| compatible = "mediatek,mt6789-cm_mgr"; | |
| required-opps = <0x23 0x24 0x25 0x26 0x27 0x28 0x29>; | |
| cm_mgr,cp_up = <0xa0 0xa0 0x32 0x64 0x64 0x64>; | |
| cm_mgr,dt_up = <0x00 0x00 0x00 0x00 0x00 0x00>; | |
| cpu_power_bcpu_weight_max = <0xc8>; | |
| interconnect-names = "cm-perf-bw"; | |
| cpu_power_bcpu_weight_min = <0x64>; | |
| cm_mgr,cp_down = <0x8c 0x8c 0x32 0x64 0x64 0x64>; | |
| use_bcpu_weight = "enable"; | |
| reg = <0x00 0xc530000 0x00 0x9000>; | |
| cm_mgr,dt_down = <0x03 0x03 0x00 0x00 0x00 0x00>; | |
| phandle = <0xe9>; | |
| interconnects = <0x22 0x01 0x22 0x00>; | |
| reg-names = "cm_mgr_base"; | |
| cm_mgr,vp_down = <0x64 0x64 0x64 0x64 0x64 0x64>; | |
| }; | |
| cpu_power_throttling { | |
| compatible = "mediatek,cpu-power-throttling"; | |
| phandle = <0x10c>; | |
| lbat_cpu_limit = <0xdbba0 0xdbba0 0x13d620>; | |
| oc_cpu_limit = <0xdbba0 0xdbba0 0x13d620>; | |
| }; | |
| opp-table-mdp0 { | |
| compatible = "operating-points-v2"; | |
| phandle = <0xb7>; | |
| opp-0 { | |
| opp-hz = <0x00 0xda64340>; | |
| opp-microvolt = <0x86470>; | |
| }; | |
| opp-1 { | |
| opp-hz = <0x00 0x14810600>; | |
| opp-microvolt = <0x927c0>; | |
| }; | |
| opp-2 { | |
| opp-hz = <0x00 0x19fcd500>; | |
| opp-microvolt = <0x9eb10>; | |
| }; | |
| opp-3 { | |
| opp-hz = <0x00 0x2367b880>; | |
| opp-microvolt = <0xb1008>; | |
| }; | |
| }; | |
| trusty { | |
| tee-name = "trusty"; | |
| tee-id = <0x00>; | |
| #size-cells = <0x02>; | |
| compatible = "android,trusty-smc-v1"; | |
| ranges; | |
| #address-cells = <0x02>; | |
| trusty-irq { | |
| compatible = "android,trusty-irq-v1"; | |
| ppi-interrupt-parent = <0x01>; | |
| }; | |
| trusty-gz-log { | |
| compatible = "android,trusty-gz-log-v1"; | |
| }; | |
| mtee { | |
| compatible = "mediatek,trusty-mtee-v1"; | |
| }; | |
| trusty-virtio { | |
| compatible = "android,trusty-virtio-v1"; | |
| }; | |
| gz-main { | |
| compatible = "mediatek,trusty-gz"; | |
| }; | |
| }; | |
| pe5 { | |
| chg_time_max = <0x1518>; | |
| tswchg_curlmt = <0xffffffff 0xffffffff 0xffffffff 0xc8 0x00 0xc8 0x12c 0x190 0xffffffff>; | |
| idvchg_ss_init = <0x3e8>; | |
| start_soc_min = <0x00>; | |
| allow_not_check_ta_status; | |
| idvchg_term = <0x1f4>; | |
| tswchg_recovery_area = <0x03>; | |
| ta_cv_ss_repeat_tmin = <0x19>; | |
| tdvchg_curlmt = <0xffffffff 0xffffffff 0xffffffff 0x12c 0x00 0x12c 0x258 0x384 0xffffffff>; | |
| polling_interval = <0x2710>; | |
| idvchg_ss_step1_vbat = <0xfa0>; | |
| swchg_aicr_ss_init = <0x190>; | |
| vbat_threshold = <0x1036>; | |
| tbat_recovery_area = <0x03>; | |
| ifod_threshold = <0xc8>; | |
| ita_cap_min = <0x3e8>; | |
| idvchg_ss_step1 = <0x64>; | |
| idvchg_step = <0x32>; | |
| gauge = <0xd3>; | |
| ita_level_dual = <0x1388 0xe74 0xd48 0xbb8>; | |
| ita_level = <0xdac 0x9c4 0x7d0 0x5dc>; | |
| compatible = "mediatek,charger,pe5"; | |
| ta_blanking = <0x190>; | |
| support_ta = "pca_ta_pps\0pd_adapter"; | |
| idvchg_ss_step = <0xfa>; | |
| tta_level_def = <0x00 0x00 0x00 0x00 0x19 0x32 0x3c 0x46 0x50>; | |
| vbat_cv = <0x10fe>; | |
| force_ta_cv_vbat = <0x109a>; | |
| swchg_off_vbat = <0x109a>; | |
| swchg_aicr = <0x00>; | |
| rcable_level = <0xfa 0x12c 0x177 0x1f4>; | |
| swchg_ichg = <0x4b0>; | |
| ircmp_vclamp = <0x96>; | |
| tswchg_level_def = <0x00 0x00 0x00 0x05 0x19 0x41 0x46 0x4b 0x50>; | |
| rcable_level_dual = <0xe6 0x15e 0x1c2 0x226>; | |
| idvchg_ss_step2_vbat = <0x1068>; | |
| vta_cap_min = <0x1a90>; | |
| vta_cap_max = <0x2af8>; | |
| tdvchg_recovery_area = <0x03>; | |
| phandle = <0x1aa>; | |
| tbat_curlmt = <0xffffffff 0xffffffff 0xffffffff 0x12c 0x00 0x258 0x384 0x41a 0xffffffff>; | |
| tdvchg_level_def = <0x00 0x00 0x00 0x05 0x19 0x37 0x3c 0x41 0x46>; | |
| swchg_aicr_ss_step = <0xc8>; | |
| tbat_level_def = <0x00 0x00 0x00 0x05 0x19 0x28 0x2b 0x2e 0x32>; | |
| idvchg_ss_step2 = <0x32>; | |
| tta_recovery_area = <0x03>; | |
| start_vbat_max = <0x10cc>; | |
| ircmp_rbat = <0x28>; | |
| tta_curlmt = <0x00 0x00 0x00 0x00 0x00 0x12c 0x258 0x384 0xffffffff>; | |
| rsw_min = <0x14>; | |
| start_soc_max = <0x50>; | |
| }; | |
| nebula { | |
| tee-name = "nebula"; | |
| tee-id = <0x01>; | |
| #size-cells = <0x02>; | |
| compatible = "android,nebula-smc-v1"; | |
| ranges; | |
| #address-cells = <0x02>; | |
| nebula-virtio { | |
| compatible = "android,nebula-virtio-v1"; | |
| }; | |
| nebula-irq { | |
| compatible = "android,nebula-irq-v1"; | |
| ppi-interrupt-parent = <0x01>; | |
| }; | |
| nebula-gz-log { | |
| compatible = "android,nebula-gz-log-v1"; | |
| }; | |
| }; | |
| cam2_inner_legacy@1a058000 { | |
| compatible = "mediatek,cam2_inner_legacy"; | |
| reg = <0x00 0x1a058000 0x00 0x8000>; | |
| }; | |
| therm_intf@00114000 { | |
| compatible = "mediatek,therm_intf"; | |
| reg = <0x00 0x114000 0x00 0x400>; | |
| phandle = <0xe3>; | |
| reg-names = "therm_sram"; | |
| }; | |
| chosen { | |
| ram_console = <0xd01100 0x80000 0x2000000 0xc00e0000>; | |
| atag,videolfb-islcm_inited = <0x00>; | |
| aee,enable = "mini"; | |
| atag,devinfo = <0xdc000000 0x00 0x00 0x00 0x400000 0x00 0x00 0x2010000 0x1000000 0x8120000 0x8120000 0x400ab56 0x40840000 0xc44401a3 0x79027276 0x91f2ab23 0x451ffe5 0x00 0xca0000 0x8120000 0x8120000 0x8120000 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x8120000 0x00 0x1000000 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x8120000 0x00 0x00 0x00 0x00 0x8120000 0x8120000 0xeeeeeeee 0x2000310 0x7248082 0x8480d4b3 0x808d481 0x6288842 0x588d073 0x4b0cd045 0x4718c4c2 0xc528d0e3 0x4680e8f3 0x00 0x00 0x00 0x00 0x00 0x00 0x7c4c1c02 0x62bc1a3f 0x5c861900 0x00 0x00 0x00 0x00 0x00 0x00 0x8120000 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x8120000 0x8120000 0x1000000 0x00 0xfc991700 0x4a29a500 0x00 0x81f84 0x81f84 0x81f84 0x12000000 0x3c 0x7a897689 0x76896689 0xe389c289 0x8b89b389 0x63896c89 0x34894d89 0xbf89ad89 0xee0a0000 0xf10a0000 0xd0b0000 0xcd08b608 0xbd0f950f 0xed08e408 0x8a0f750f 0x6900b600 0x170a990c 0x8709a40c 0x8120000 0x8120000 0x8120000 0x00 0x00 0x40 0x00 0x00 0xed86d5 0x65 0x55f608e0 0xf818e0 0xe0f8f800 0x3812700 0x00 0x8120000 0x8120000 0x8120000 0x8120000 0x8120000 0x8120000 0x8120000 0x8120000 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x3f000000 0x7030 0x1316186f 0x00 0x00 0x00 0x00 0x00 0x3c07be08 0x5807cb08 0x58027601 0x00 0x00 0x8120000 0x8120000 0x8120000 0x8120000 0x8120000 0x8120000 0x8120000 0x8120000 0x8120000 0x8120000 0x8120000 0x8120000 0x8120000 0x8120000 0x8120000 0x8120000 0x8120000 0xfa0a0000 0x150b0000 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x8120000 0x6221678 0x2367014 0x34a1b312 0x910310be 0x9f1d4669 0xad81f1f3 0x63ee0832 0x43534b5>; | |
| linux,initrd-start = <0x66f00000>; | |
| atag,videolfb-fb_base_l = <0xfeac6000>; | |
| atag,videolfb-islcmfound = <0x01>; | |
| atag,boot = <0x10000000 0x2080041 0x00 0x2000000>; | |
| atag,videolfb-lcmname = "nt36672e_fhdp_dsi_vdo_60hz_jdi_dphy_drv"; | |
| mrdump,lk = "MRDUMP11"; | |
| atag,videolfb = <0x60acfe 0x00 0x1000000 0x88170000 0x4601 0x6a74795f 0x36373839 0x5f667438 0x3730375f 0x6668645f 0x345f3430 0x70696e5f 0x6c636d5f 0x64727600 0x1878f550>; | |
| kaslr-seed = <0x00 0x00>; | |
| phandle = <0x50>; | |
| atag,videolfb-fb_base_h = <0x00>; | |
| atag,masp = <0x58000000 0x66080041 0x11000000 0x22000000 0x00 0x1000000 0x384b43ef 0xba536032 0xfca6dd7e 0xf9294322 0x31413532 0x41333637 0x43423132 0x43343538 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; | |
| atag,chipid = <0x18000000 0x8120000 0x8a0000 0xca0000 0x00>; | |
| mrdump,ddr_rsv = "yes"; | |
| linux,initrd-end = <0x685c49c1>; | |
| mrdump,cblock = <0x48082000 0x8000>; | |
| bootargs = " console=tty0 root=/dev/ram loglevel=8 8250.nr_uarts=4 initcall_debug=1 transparent_hugepage=never vmalloc=400M swiotlb=noforce cma=64M firmware_class.path=/vendor/firmware pelt=8 loop.max_part=7 earlycon=uart8250,mmio32,0x11002000 console=ttyS0,921600n1 mtk_printk_ctrl.disable_uart=0 has_battery_removed=1 ramoops.mem_address=0x48090000 ramoops.mem_size=0xe0000 ramoops.pmsg_size=0x10000 ramoops.console_size=0x40000 usb2jtag_mode=0 root=/dev/ram bootopt=64S3,32N2,64N2 arm64.nomte bootconfig"; | |
| log_store = <0xdf1100 0x10000>; | |
| atag,videolfb-fps = <0x1770>; | |
| atag,videolfb-vramSize = <0x1460000>; | |
| }; | |
| psci { | |
| compatible = "arm,psci-1.0"; | |
| method = "smc"; | |
| }; | |
| syscon@1101B000 { | |
| compatible = "mediatek,mt6789-imp_iic_wrap_c\0syscon"; | |
| reg = <0x00 0x1101b000 0x00 0x1000>; | |
| phandle = <0x3a>; | |
| #clock-cells = <0x01>; | |
| }; | |
| utos_tester { | |
| compatible = "microtrust,tester-v1"; | |
| }; | |
| soc { | |
| #size-cells = <0x02>; | |
| compatible = "simple-bus"; | |
| ranges; | |
| #address-cells = <0x02>; | |
| sej@1000a000 { | |
| compatible = "mediatek,sej"; | |
| reg = <0x00 0x1000a000 0x00 0x1000>; | |
| interrupts = <0x00 0x106 0x04 0x00>; | |
| }; | |
| disp_mutex@14001000 { | |
| compatible = "mediatek,disp_mutex0\0mediatek,mt6789-disp-mutex"; | |
| reg = <0x00 0x14001000 0x00 0x1000>; | |
| clocks = <0x35 0x00>; | |
| phandle = <0x17f>; | |
| interrupts = <0x00 0x11d 0x04 0x00>; | |
| }; | |
| MD1_SIM2_HOT_PLUG_EINT { | |
| phandle = <0x14d>; | |
| }; | |
| smi_larb9@1502e000 { | |
| clock-names = "apb\0smi"; | |
| compatible = "mediatek,smi_larb9\0mediatek,mt6789-smi-larb\0mediatek,smi-larb"; | |
| mediatek,smi = <0xa1>; | |
| mediatek,larb-id = <0x09>; | |
| reg = <0x00 0x1502e000 0x00 0x1000>; | |
| clocks = <0x34 0x00 0x34 0x00>; | |
| phandle = <0x98>; | |
| power-domains = <0x2d 0x06>; | |
| }; | |
| smi_larb1@14004000 { | |
| clock-names = "apb\0smi\0gals0\0gals1"; | |
| compatible = "mediatek,smi_larb1\0mediatek,mt6789-smi-larb\0mediatek,smi-larb"; | |
| mediatek,smi = <0x9b>; | |
| mediatek,larb-id = <0x01>; | |
| reg = <0x00 0x14004000 0x00 0x1000>; | |
| clocks = <0x35 0x0a 0x35 0x0f 0x35 0x13 0x35 0x14>; | |
| phandle = <0x94>; | |
| power-domains = <0x2d 0x0a>; | |
| init-power-on; | |
| }; | |
| kp@10010000 { | |
| clock-names = "kpd"; | |
| mediatek,key-debounce-ms = <0x400>; | |
| mediatek,pwrkey-eint-gpio = <0x00>; | |
| mediatek,sw-rstkey = <0x66>; | |
| compatible = "mediatek,kp"; | |
| status = "okay"; | |
| mediatek,use-extend-type = <0x00>; | |
| reg = <0x00 0x10010000 0x00 0x1000>; | |
| mediatek,hw-map-num = <0x48>; | |
| clocks = <0x55>; | |
| phandle = <0xd0>; | |
| mediatek,pwkey-gpio-din = <0x00>; | |
| mediatek,hw-rstkey = <0x11>; | |
| mediatek,hw-dl-key2 = <0x08>; | |
| mediatek,hw-init-map = <0x73 0x72 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; | |
| interrupts = <0x00 0x6a 0x01 0x00>; | |
| mediatek,sw-pwrkey = <0x74>; | |
| mediatek,hw-pwrkey = <0x08>; | |
| mediatek,key-debounce = <0x400>; | |
| }; | |
| mdp_rdma0@1f003000 { | |
| clock-names = "MDP_RDMA0"; | |
| compatible = "mediatek,mdp_rdma0"; | |
| reg = <0x00 0x1f003000 0x00 0x1000>; | |
| clocks = <0x2c 0x00>; | |
| phandle = <0xaf>; | |
| }; | |
| pwrap@10026000 { | |
| clock-names = "spi\0wrap\0ulposc\0ulposc_osc"; | |
| compatible = "mediatek,mt6789-pwrap"; | |
| reg = <0x00 0x10026000 0x00 0x1000>; | |
| clocks = <0x2b 0x01 0x2b 0x00 0x2a 0x18 0x2a 0x88>; | |
| phandle = <0x54>; | |
| reg-names = "pwrap"; | |
| interrupts = <0x00 0xfc 0x04>; | |
| mt6366 { | |
| compatible = "mediatek,mt6366"; | |
| #interrupt-cells = <0x02>; | |
| interrupt-parent = <0x49>; | |
| phandle = <0xab>; | |
| interrupt-controller; | |
| interrupts = <0x89 0x04 0x89 0x00>; | |
| mt63xx_debug { | |
| compatible = "mediatek,mt63xx-debug"; | |
| }; | |
| mt6366keys { | |
| compatible = "mediatek,mt6366-keys"; | |
| power-off-time-sec = <0x00>; | |
| phandle = <0x11d>; | |
| mediatek,long-press-mode = <0x01>; | |
| power { | |
| linux,keycodes = <0x74>; | |
| wakeup-source; | |
| }; | |
| home { | |
| linux,keycodes = <0x13a>; | |
| }; | |
| }; | |
| accdet { | |
| io-channel-names = "pmic_accdet"; | |
| accdet-mic-vol = <0x06>; | |
| headset-four-key-threshold = <0x00 0x3a 0x79 0xc0 0x190>; | |
| mediatek,accdet-pmic = <0x66>; | |
| nvmem-names = "mt63xx-accdet-efuse"; | |
| nvmem = <0x4d>; | |
| compatible = "mediatek,mt6358-accdet"; | |
| headset-mode-setting = <0x500 0x500 0x01 0x1f0 0x800 0x800 0x20 0x44 0x00 0x00 0x0e 0x00 0x00 0x00 0x00 0x00>; | |
| status = "okay"; | |
| accdet-plugout-debounce = <0x01>; | |
| accdet-name = "mt6358-accdet"; | |
| headset-three-key-threshold = <0x00 0x50 0xdc 0x190>; | |
| io-channels = <0x19 0x09>; | |
| headset-eint-level-pol = <0x08>; | |
| phandle = <0x11c>; | |
| headset-three-key-threshold-CDD = <0x00 0x79 0xc0 0x258>; | |
| accdet-mic-mode = <0x01>; | |
| }; | |
| mt6358codec { | |
| io-channel-names = "pmic_hpofs_cal"; | |
| mediatek,dmic-mode = <0x00>; | |
| nvmem-names = "pmic-hp-efuse"; | |
| reg_vaud28-supply = <0x4f>; | |
| nvmem = <0x4d>; | |
| compatible = "mediatek,mt6366-sound"; | |
| io-channels = <0x19 0x0c>; | |
| phandle = <0x142>; | |
| mediatek,mic-type = <0x01>; | |
| }; | |
| mt6358regulator { | |
| compatible = "mediatek,mt6358-regulator"; | |
| phandle = <0x11e>; | |
| ldo_vcama2 { | |
| regulator-min-microvolt = <0x1b7740>; | |
| phandle = <0x13a>; | |
| regulator-enable-ramp-delay = <0x145>; | |
| regulator-max-microvolt = <0x2dc6c0>; | |
| regulator-name = "vcama2"; | |
| }; | |
| buck_vproc12 { | |
| regulator-min-microvolt = <0x7a120>; | |
| regulator-always-on; | |
| phandle = <0x3f>; | |
| regulator-enable-ramp-delay = <0xc8>; | |
| regulator-allowed-modes = <0x00 0x01>; | |
| regulator-max-microvolt = <0x13bdb6>; | |
| regulator-name = "vproc12"; | |
| }; | |
| ldo_vio28 { | |
| regulator-min-microvolt = <0x2ab980>; | |
| regulator-always-on; | |
| compatible = "regulator-fixed"; | |
| phandle = <0x135>; | |
| regulator-enable-ramp-delay = <0x10e>; | |
| regulator-max-microvolt = <0x2ab980>; | |
| regulator-name = "vio28"; | |
| }; | |
| ldo_vsram_proc11 { | |
| regulator-min-microvolt = <0x7a120>; | |
| regulator-always-on; | |
| phandle = <0x12b>; | |
| regulator-enable-ramp-delay = <0xf0>; | |
| regulator-max-microvolt = <0x13bdb6>; | |
| regulator-name = "vsram_proc11"; | |
| }; | |
| ldo_vcn28 { | |
| regulator-min-microvolt = <0x2ab980>; | |
| regulator-always-on; | |
| compatible = "regulator-fixed"; | |
| phandle = <0x12c>; | |
| regulator-enable-ramp-delay = <0x10e>; | |
| regulator-max-microvolt = <0x2ab980>; | |
| regulator-name = "vcn28"; | |
| }; | |
| ldo_vrf18 { | |
| regulator-min-microvolt = <0x1b7740>; | |
| compatible = "regulator-fixed"; | |
| phandle = <0x137>; | |
| regulator-enable-ramp-delay = <0x78>; | |
| regulator-max-microvolt = <0x1b7740>; | |
| regulator-name = "vrf18"; | |
| }; | |
| ldo_vdram2 { | |
| regulator-min-microvolt = <0x927c0>; | |
| regulator-always-on; | |
| phandle = <0x122>; | |
| regulator-enable-ramp-delay = <0xce4>; | |
| regulator-max-microvolt = <0x1b7740>; | |
| regulator-name = "vdram2"; | |
| }; | |
| VMCH_EINT_LOW { | |
| regulator-min-microvolt = <0x2c4020>; | |
| phandle = <0x88>; | |
| regulator-enable-ramp-delay = <0x3c>; | |
| regulator-max-microvolt = <0x325aa0>; | |
| regulator-name = "mt6358_vmch_eint_low"; | |
| }; | |
| ldo_vefuse { | |
| regulator-min-microvolt = <0x19f0a0>; | |
| phandle = <0x12f>; | |
| regulator-enable-ramp-delay = <0x10e>; | |
| regulator-max-microvolt = <0x1cfde0>; | |
| regulator-name = "vefuse"; | |
| }; | |
| ldo_vrf12 { | |
| regulator-min-microvolt = <0x124f80>; | |
| compatible = "regulator-fixed"; | |
| phandle = <0x124>; | |
| regulator-enable-ramp-delay = <0x78>; | |
| regulator-max-microvolt = <0x124f80>; | |
| regulator-name = "vrf12"; | |
| }; | |
| ldo_vcn33_bt { | |
| regulator-min-microvolt = <0x325aa0>; | |
| phandle = <0x138>; | |
| regulator-enable-ramp-delay = <0x10e>; | |
| regulator-max-microvolt = <0x3567e0>; | |
| regulator-name = "vcn33_bt"; | |
| }; | |
| ldo_vmc { | |
| regulator-min-microvolt = <0x1b7740>; | |
| phandle = <0x89>; | |
| regulator-enable-ramp-delay = <0x3c>; | |
| regulator-max-microvolt = <0x325aa0>; | |
| regulator-name = "vmc"; | |
| }; | |
| ldo_va12 { | |
| regulator-min-microvolt = <0x124f80>; | |
| regulator-always-on; | |
| compatible = "regulator-fixed"; | |
| phandle = <0x136>; | |
| regulator-enable-ramp-delay = <0x10e>; | |
| regulator-max-microvolt = <0x124f80>; | |
| regulator-name = "va12"; | |
| }; | |
| buck_vdram1 { | |
| regulator-min-microvolt = <0x7a120>; | |
| regulator-always-on; | |
| phandle = <0x11f>; | |
| regulator-enable-ramp-delay = <0x00>; | |
| regulator-allowed-modes = <0x00 0x01>; | |
| regulator-max-microvolt = <0x1fda4c>; | |
| regulator-name = "vdram1"; | |
| }; | |
| ldo_vldo28 { | |
| regulator-min-microvolt = <0x2ab980>; | |
| phandle = <0x13b>; | |
| regulator-enable-ramp-delay = <0x10e>; | |
| regulator-max-microvolt = <0x2dc6c0>; | |
| regulator-name = "vldo28"; | |
| }; | |
| buck_vcore_sshub { | |
| regulator-min-microvolt = <0x7a120>; | |
| phandle = <0x59>; | |
| regulator-max-microvolt = <0x13bdb6>; | |
| regulator-name = "vcore_sshub"; | |
| }; | |
| ldo_vsram_others { | |
| regulator-min-microvolt = <0x7a120>; | |
| regulator-always-on; | |
| phandle = <0x12d>; | |
| regulator-enable-ramp-delay = <0xf0>; | |
| regulator-max-microvolt = <0x13bdb6>; | |
| regulator-name = "vsram_others"; | |
| }; | |
| ldo_vcamd { | |
| regulator-min-microvolt = <0xdbba0>; | |
| phandle = <0x128>; | |
| regulator-enable-ramp-delay = <0x145>; | |
| regulator-max-microvolt = <0x1b7740>; | |
| regulator-name = "vcamd"; | |
| }; | |
| ldo_vsram_others_sshub { | |
| regulator-min-microvolt = <0x7a120>; | |
| phandle = <0x5a>; | |
| regulator-max-microvolt = <0x13bdb6>; | |
| regulator-name = "vsram_others_sshub"; | |
| }; | |
| ldo_vbif28 { | |
| regulator-min-microvolt = <0x2ab980>; | |
| regulator-always-on; | |
| compatible = "regulator-fixed"; | |
| phandle = <0x132>; | |
| regulator-enable-ramp-delay = <0x10e>; | |
| regulator-max-microvolt = <0x2ab980>; | |
| regulator-name = "vbif28"; | |
| }; | |
| ldo_vaud28 { | |
| regulator-min-microvolt = <0x2ab980>; | |
| regulator-always-on; | |
| compatible = "regulator-fixed"; | |
| phandle = <0x4f>; | |
| regulator-enable-ramp-delay = <0x10e>; | |
| regulator-max-microvolt = <0x2ab980>; | |
| regulator-name = "vaud28"; | |
| }; | |
| ldo_vxo22 { | |
| regulator-min-microvolt = <0x2191c0>; | |
| regulator-always-on; | |
| compatible = "regulator-fixed"; | |
| phandle = <0x12e>; | |
| regulator-enable-ramp-delay = <0x78>; | |
| regulator-max-microvolt = <0x2191c0>; | |
| regulator-name = "vxo22"; | |
| }; | |
| ldo_vcama1 { | |
| regulator-min-microvolt = <0x1b7740>; | |
| phandle = <0x134>; | |
| regulator-enable-ramp-delay = <0x145>; | |
| regulator-max-microvolt = <0x2dc6c0>; | |
| regulator-name = "vcama1"; | |
| }; | |
| ldo_vsram_core { | |
| regulator-min-microvolt = <0x7a120>; | |
| regulator-always-on; | |
| phandle = <0x5e>; | |
| regulator-enable-ramp-delay = <0xf0>; | |
| regulator-max-microvolt = <0x13bdb6>; | |
| regulator-name = "vsram_core"; | |
| }; | |
| ldo_vsram_proc12 { | |
| regulator-min-microvolt = <0x7a120>; | |
| regulator-always-on; | |
| phandle = <0x133>; | |
| regulator-enable-ramp-delay = <0xf0>; | |
| regulator-max-microvolt = <0x13bdb6>; | |
| regulator-name = "vsram_proc12"; | |
| }; | |
| ldo_vcn18 { | |
| regulator-min-microvolt = <0x1b7740>; | |
| compatible = "regulator-fixed"; | |
| phandle = <0x129>; | |
| regulator-enable-ramp-delay = <0x10e>; | |
| regulator-max-microvolt = <0x1b7740>; | |
| regulator-name = "vcn18"; | |
| }; | |
| ldo_vio18 { | |
| regulator-min-microvolt = <0x1b7740>; | |
| regulator-always-on; | |
| compatible = "regulator-fixed"; | |
| phandle = <0x125>; | |
| regulator-enable-ramp-delay = <0xa8c>; | |
| regulator-max-microvolt = <0x1b7740>; | |
| regulator-name = "vio18"; | |
| }; | |
| buck_vs1 { | |
| regulator-min-microvolt = <0xf4240>; | |
| regulator-always-on; | |
| phandle = <0x121>; | |
| regulator-enable-ramp-delay = <0x00>; | |
| regulator-max-microvolt = <0x277b6c>; | |
| regulator-name = "vs1"; | |
| }; | |
| ldo_vcamio { | |
| regulator-min-microvolt = <0x1b7740>; | |
| compatible = "regulator-fixed"; | |
| phandle = <0x127>; | |
| regulator-enable-ramp-delay = <0x145>; | |
| regulator-max-microvolt = <0x1b7740>; | |
| regulator-name = "vcamio"; | |
| }; | |
| buck_vgpu { | |
| regulator-min-microvolt = <0x7a120>; | |
| phandle = <0x8d>; | |
| regulator-enable-ramp-delay = <0xc8>; | |
| regulator-allowed-modes = <0x00 0x01>; | |
| regulator-max-microvolt = <0x13bdb6>; | |
| regulator-name = "vgpu"; | |
| }; | |
| buck_vcore { | |
| regulator-min-microvolt = <0x7a120>; | |
| regulator-always-on; | |
| phandle = <0x56>; | |
| regulator-enable-ramp-delay = <0xc8>; | |
| regulator-allowed-modes = <0x00 0x01>; | |
| regulator-max-microvolt = <0x13bdb6>; | |
| regulator-name = "vcore"; | |
| }; | |
| ldo_va09 { | |
| regulator-min-microvolt = <0xdbba0>; | |
| compatible = "regulator-fixed"; | |
| phandle = <0x13d>; | |
| regulator-enable-ramp-delay = <0x108>; | |
| regulator-max-microvolt = <0xdbba0>; | |
| regulator-name = "va09"; | |
| }; | |
| ldo_vusb { | |
| regulator-min-microvolt = <0x2dc6c0>; | |
| regulator-always-on; | |
| phandle = <0x126>; | |
| regulator-enable-ramp-delay = <0x10e>; | |
| regulator-max-microvolt = <0x2f4d60>; | |
| regulator-name = "vusb"; | |
| }; | |
| ldo_vaux18 { | |
| regulator-min-microvolt = <0x1b7740>; | |
| regulator-always-on; | |
| compatible = "regulator-fixed"; | |
| phandle = <0x130>; | |
| regulator-enable-ramp-delay = <0x10e>; | |
| regulator-max-microvolt = <0x1b7740>; | |
| regulator-name = "vaux18"; | |
| }; | |
| ldo_vsram_gpu { | |
| regulator-min-microvolt = <0x7a120>; | |
| phandle = <0x8e>; | |
| regulator-enable-ramp-delay = <0xf0>; | |
| regulator-max-microvolt = <0x13bdb6>; | |
| regulator-name = "vsram_gpu"; | |
| }; | |
| ldo_vsim2 { | |
| regulator-min-microvolt = <0x00>; | |
| phandle = <0x13c>; | |
| regulator-enable-ramp-delay = <0x21c>; | |
| regulator-max-microvolt = <0x2f4d60>; | |
| regulator-name = "vsim2"; | |
| }; | |
| buck_vmodem { | |
| regulator-min-microvolt = <0x7a120>; | |
| regulator-always-on; | |
| phandle = <0x5d>; | |
| regulator-enable-ramp-delay = <0x384>; | |
| regulator-allowed-modes = <0x00 0x01>; | |
| regulator-max-microvolt = <0x13bdb6>; | |
| regulator-name = "vmodem"; | |
| }; | |
| VMCH_EINT_HIGH { | |
| regulator-min-microvolt = <0x2c4020>; | |
| phandle = <0x13e>; | |
| regulator-enable-ramp-delay = <0x3c>; | |
| regulator-max-microvolt = <0x325aa0>; | |
| regulator-name = "mt6358_vmch_eint_high"; | |
| }; | |
| ldo_vsim1 { | |
| regulator-min-microvolt = <0x00>; | |
| phandle = <0x123>; | |
| regulator-enable-ramp-delay = <0x21c>; | |
| regulator-max-microvolt = <0x2f4d60>; | |
| regulator-name = "vsim1"; | |
| }; | |
| ldo_vcn33_wifi { | |
| regulator-min-microvolt = <0x325aa0>; | |
| phandle = <0x139>; | |
| regulator-enable-ramp-delay = <0x10e>; | |
| regulator-max-microvolt = <0x3567e0>; | |
| regulator-name = "vcn33_wifi"; | |
| }; | |
| ldo_vibr { | |
| regulator-min-microvolt = <0x124f80>; | |
| phandle = <0x48>; | |
| regulator-enable-ramp-delay = <0x3c>; | |
| regulator-max-microvolt = <0x325aa0>; | |
| regulator-name = "vibr"; | |
| }; | |
| ldo_vmch { | |
| regulator-min-microvolt = <0x2c4020>; | |
| phandle = <0x131>; | |
| regulator-enable-ramp-delay = <0x3c>; | |
| regulator-max-microvolt = <0x325aa0>; | |
| regulator-name = "vmch"; | |
| }; | |
| buck_vproc11 { | |
| regulator-min-microvolt = <0x7a120>; | |
| regulator-always-on; | |
| phandle = <0x3e>; | |
| regulator-enable-ramp-delay = <0xc8>; | |
| regulator-allowed-modes = <0x00 0x01>; | |
| regulator-max-microvolt = <0x13bdb6>; | |
| regulator-name = "vproc11"; | |
| }; | |
| ldo_vfe28 { | |
| regulator-min-microvolt = <0x2ab980>; | |
| compatible = "regulator-fixed"; | |
| phandle = <0x12a>; | |
| regulator-enable-ramp-delay = <0x10e>; | |
| regulator-max-microvolt = <0x2ab980>; | |
| regulator-name = "vfe28"; | |
| }; | |
| buck_vs2 { | |
| regulator-min-microvolt = <0x7a120>; | |
| regulator-always-on; | |
| phandle = <0x120>; | |
| regulator-enable-ramp-delay = <0x00>; | |
| regulator-max-microvolt = <0x1fda4c>; | |
| regulator-name = "vs2"; | |
| }; | |
| ldo_vemc { | |
| regulator-min-microvolt = <0x2c4020>; | |
| phandle = <0x81>; | |
| regulator-enable-ramp-delay = <0x3c>; | |
| regulator-max-microvolt = <0x325aa0>; | |
| regulator-name = "vemc"; | |
| }; | |
| }; | |
| pmic_lbat_service { | |
| compatible = "mediatek,mt6358-lbat_service"; | |
| phandle = <0x141>; | |
| }; | |
| mt6358-efuse { | |
| #size-cells = <0x01>; | |
| compatible = "mediatek,mt6358-efuse"; | |
| #address-cells = <0x01>; | |
| phandle = <0x4d>; | |
| mt6366_e_data { | |
| reg = <0x40 0x0c>; | |
| phandle = <0x1a>; | |
| }; | |
| }; | |
| mt6358rtc { | |
| #size-cells = <0x01>; | |
| compatible = "mediatek,mt6358-rtc"; | |
| #address-cells = <0x01>; | |
| phandle = <0x143>; | |
| ext_32k { | |
| bits = <0x06 0x01>; | |
| reg = <0x02 0x01>; | |
| phandle = <0x144>; | |
| }; | |
| fg_init { | |
| reg = <0x00 0x01>; | |
| phandle = <0x51>; | |
| }; | |
| fg_soc { | |
| reg = <0x01 0x01>; | |
| phandle = <0x52>; | |
| }; | |
| }; | |
| mt635x-auxadc { | |
| cali-efuse-offset = <0x01>; | |
| nvmem-names = "auxadc_efuse_dev"; | |
| nvmem = <0x4d>; | |
| compatible = "mediatek,pmic-auxadc\0mediatek,mt6358-auxadc"; | |
| phandle = <0x19>; | |
| #io-channel-cells = <0x01>; | |
| hpofs_cal { | |
| channel = <0x0c>; | |
| avg-num = <0x100>; | |
| }; | |
| vcdt { | |
| channel = <0x02>; | |
| }; | |
| dcxo_temp { | |
| channel = <0x0d>; | |
| avg-num = <0x10>; | |
| }; | |
| batadc { | |
| channel = <0x00>; | |
| avg-num = <0x80>; | |
| resistance-ratio = <0x03 0x01>; | |
| }; | |
| imix_r { | |
| channel = <0x10>; | |
| val = <0x66>; | |
| }; | |
| vbif { | |
| channel = <0x0e>; | |
| resistance-ratio = <0x02 0x01>; | |
| }; | |
| accdet { | |
| channel = <0x09>; | |
| }; | |
| vproc_temp { | |
| channel = <0x07>; | |
| }; | |
| tsx_temp { | |
| channel = <0x0b>; | |
| avg-num = <0x80>; | |
| }; | |
| chip_temp { | |
| channel = <0x05>; | |
| }; | |
| imp { | |
| channel = <0x0f>; | |
| avg-num = <0x80>; | |
| resistance-ratio = <0x03 0x01>; | |
| }; | |
| dcxo_volt { | |
| channel = <0x0a>; | |
| resistance-ratio = <0x03 0x02>; | |
| }; | |
| vgpu_temp { | |
| channel = <0x08>; | |
| }; | |
| bat_temp { | |
| channel = <0x03>; | |
| resistance-ratio = <0x02 0x01>; | |
| }; | |
| vcore_temp { | |
| channel = <0x06>; | |
| }; | |
| }; | |
| mtk_battery_oc_throttling { | |
| oc-thd-h = <0x173e>; | |
| oc-thd-l = <0x1b58>; | |
| compatible = "mediatek,mt6358-battery_oc_throttling"; | |
| phandle = <0x145>; | |
| }; | |
| mtk_gauge { | |
| g_FG_PSEUDO100_T3 = <0x64>; | |
| io-channel-names = "pmic_battery_temp\0pmic_battery_voltage\0pmic_bif_voltage\0pmic_ptim_voltage\0pmic_ptim_r"; | |
| g_FG_charge_PSEUDO100 = <0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64>; | |
| Q_MAX_SYS_VOLTAGE_BAT1 = <0xd16>; | |
| R_FG_VALUE = <0x05>; | |
| g_FG_PSEUDO100_row = <0x04>; | |
| Q_MAX_SYS_VOLTAGE_BAT0 = <0xd16>; | |
| battery0_profile_t1_num = <0x5f>; | |
| COM_R_FG_VALUE = <0x00>; | |
| PMIC_SHUTDOWN_CURRENT = <0x14>; | |
| TEMPERATURE_T2 = <0x0a>; | |
| Q_MAX_SYS_VOLTAGE_BAT2 = <0xd16>; | |
| battery0_profile_t0_col = <0x03>; | |
| KEEP_100_PERCENT = <0x01>; | |
| g_PON_SYS_IBOOT_row = <0x04>; | |
| battery0_profile_t0_num = <0x5f>; | |
| TEMPERATURE_T1 = <0x19>; | |
| shutdown_time = <0x02>; | |
| g_FG_PSEUDO100 = <0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64 0x64>; | |
| compatible = "mediatek,mt6358-gauge"; | |
| RBAT_PULL_UP_VOLT = <0xaf0>; | |
| battery0_profile_t3_num = <0x5f>; | |
| battery0_profile_t5 = <0x00 0xa8a6 0x51e 0x23e 0xa802 0x51e 0x47c 0xa7c6 0x526 0x6ba 0xa77f 0x526 0x8f8 0xa731 0x526 0xb36 0xa6e6 0x529 0xd74 0xa671 0x52a 0xfb2 0xa5fe 0x526 0x11f0 0xa58b 0x526 0x142e 0xa519 0x522 0x166c 0xa4a6 0x526 0x18aa 0xa439 0x52d 0x1ae8 0xa3c7 0x52e 0x1d26 0xa357 0x52d 0x1f64 0xa2e4 0x52d 0x21a2 0xa278 0x52e 0x23e0 0xa20b 0x538 0x261e 0xa19f 0x53d 0x285c 0xa132 0x53c 0x2a9a 0xa0c9 0x545 0x2cd8 0xa05c 0x540 0x2f16 0x9ff9 0x54c 0x3154 0x9f90 0x550 0x3392 0x9f29 0x558 0x35d0 0x9ec6 0x563 0x380e 0x9e63 0x568 0x3a4c 0x9e00 0x56f 0x3c8a 0x9d9d 0x573 0x3ec8 0x9d40 0x57c 0x4106 0x9cdc 0x57b 0x4344 0x9c79 0x57b 0x4582 0x9c16 0x57b 0x47c0 0x9bb6 0x57b 0x49fe 0x9b4c 0x577 0x4c3c 0x9ae6 0x573 0x4e7a 0x9a7a 0x56f 0x50b8 0x9a0d 0x564 0x52f6 0x999a 0x558 0x5534 0x992b 0x549 0x5772 0x98c1 0x538 0x59b0 0x986b 0x536 0x5bee 0x9817 0x52d 0x5e2c 0x97cc 0x529 0x606a 0x9788 0x52d 0x62a8 0x9747 0x529 0x64e6 0x9709 0x531 0x6724 0x96d1 0x535 0x6962 0x9696 0x535 0x6ba0 0x9662 0x53a 0x6dde 0x962d 0x53a 0x701c 0x95f8 0x53c 0x725a 0x95ca 0x545 0x7498 0x9598 0x549 0x76d6 0x956d 0x550 0x7914 0x9541 0x558 0x7b52 0x9513 0x55d 0x7d90 0x94eb 0x564 0x7fce 0x94c2 0x567 0x820c 0x9497 0x568 0x844a 0x9475 0x56f 0x8688 0x944d 0x56f 0x88c6 0x942a 0x577 0x8b04 0x9402 0x573 0x8d42 0x93e0 0x577 0x8f80 0x93be 0x577 0x91be 0x939f 0x583 0x93fc 0x937a 0x580 0x963a 0x935b 0x58b 0x9878 0x9339 0x58f 0x9ab6 0x931a 0x59a 0x9cf4 0x92f4 0x5a1 0x9f32 0x92cf 0x5a9 0xa170 0x92a7 0x5b9 0xa3ae 0x927c 0x5c2 0xa5ec 0x9253 0x5d7 0xa82a 0x9225 0x5e7 0xaa68 0x91f0 0x5f3 0xaca6 0x91b8 0x60a 0xaee4 0x917a 0x621 0xb122 0x9136 0x631 0xb360 0x90f2 0x650 0xb59e 0x90a7 0x65f 0xb7dc 0x9063 0x67b 0xba1a 0x902b 0x69d 0xbc58 0x9006 0x6cc 0xbe96 0x8fe7 0x6fe 0xc0d4 0x8fc2 0x731 0xc312 0x8f90 0x776 0xc550 0x8f3d 0x7c1 0xc78e 0x8eb7 0x80a 0xc9cc 0x8dd2 0x841 0xcc0a 0x8c61 0x873 0xce48 0x8a58 0x8c4 0xd086 0x878c 0x943 0xd2c4 0x84aa 0x99c>; | |
| PMIC_MIN_VOL = <0x82dc>; | |
| battery0_profile_t4_num = <0x5f>; | |
| fg_swocv_v = <0x9e68>; | |
| TEMPERATURE_T3 = <0x00>; | |
| nvmem-cell-names = "initialization\0state-of-charge"; | |
| battery0_profile_t4 = <0x00 0xa8a6 0x51e 0x23e 0xa802 0x51e 0x47c 0xa7c6 0x526 0x6ba 0xa77f 0x526 0x8f8 0xa731 0x526 0xb36 0xa6e6 0x529 0xd74 0xa671 0x52a 0xfb2 0xa5fe 0x526 0x11f0 0xa58b 0x526 0x142e 0xa519 0x522 0x166c 0xa4a6 0x526 0x18aa 0xa439 0x52d 0x1ae8 0xa3c7 0x52e 0x1d26 0xa357 0x52d 0x1f64 0xa2e4 0x52d 0x21a2 0xa278 0x52e 0x23e0 0xa20b 0x538 0x261e 0xa19f 0x53d 0x285c 0xa132 0x53c 0x2a9a 0xa0c9 0x545 0x2cd8 0xa05c 0x540 0x2f16 0x9ff9 0x54c 0x3154 0x9f90 0x550 0x3392 0x9f29 0x558 0x35d0 0x9ec6 0x563 0x380e 0x9e63 0x568 0x3a4c 0x9e00 0x56f 0x3c8a 0x9d9d 0x573 0x3ec8 0x9d40 0x57c 0x4106 0x9cdc 0x57b 0x4344 0x9c79 0x57b 0x4582 0x9c16 0x57b 0x47c0 0x9bb6 0x57b 0x49fe 0x9b4c 0x577 0x4c3c 0x9ae6 0x573 0x4e7a 0x9a7a 0x56f 0x50b8 0x9a0d 0x564 0x52f6 0x999a 0x558 0x5534 0x992b 0x549 0x5772 0x98c1 0x538 0x59b0 0x986b 0x536 0x5bee 0x9817 0x52d 0x5e2c 0x97cc 0x529 0x606a 0x9788 0x52d 0x62a8 0x9747 0x529 0x64e6 0x9709 0x531 0x6724 0x96d1 0x535 0x6962 0x9696 0x535 0x6ba0 0x9662 0x53a 0x6dde 0x962d 0x53a 0x701c 0x95f8 0x53c 0x725a 0x95ca 0x545 0x7498 0x9598 0x549 0x76d6 0x956d 0x550 0x7914 0x9541 0x558 0x7b52 0x9513 0x55d 0x7d90 0x94eb 0x564 0x7fce 0x94c2 0x567 0x820c 0x9497 0x568 0x844a 0x9475 0x56f 0x8688 0x944d 0x56f 0x88c6 0x942a 0x577 0x8b04 0x9402 0x573 0x8d42 0x93e0 0x577 0x8f80 0x93be 0x577 0x91be 0x939f 0x583 0x93fc 0x937a 0x580 0x963a 0x935b 0x58b 0x9878 0x9339 0x58f 0x9ab6 0x931a 0x59a 0x9cf4 0x92f4 0x5a1 0x9f32 0x92cf 0x5a9 0xa170 0x92a7 0x5b9 0xa3ae 0x927c 0x5c2 0xa5ec 0x9253 0x5d7 0xa82a 0x9225 0x5e7 0xaa68 0x91f0 0x5f3 0xaca6 0x91b8 0x60a 0xaee4 0x917a 0x621 0xb122 0x9136 0x631 0xb360 0x90f2 0x650 0xb59e 0x90a7 0x65f 0xb7dc 0x9063 0x67b 0xba1a 0x902b 0x69d 0xbc58 0x9006 0x6cc 0xbe96 0x8fe7 0x6fe 0xc0d4 0x8fc2 0x731 0xc312 0x8f90 0x776 0xc550 0x8f3d 0x7c1 0xc78e 0x8eb7 0x80a 0xc9cc 0x8dd2 0x841 0xcc0a 0x8c61 0x873 0xce48 0x8a58 0x8c4 0xd086 0x878c 0x943 0xd2c4 0x84aa 0x99c>; | |
| ACTIVE_TABLE = <0x06>; | |
| g_PMIC_MIN_VOL_col = <0x0a>; | |
| g_PON_SYS_IBOOT_col = <0x0a>; | |
| nvmem-cells = <0x51 0x52>; | |
| EMBEDDED_SEL = <0x00>; | |
| fg_swocv_i = <0xfffff619>; | |
| g_QMAX_SYS_VOL = <0x8886 0x8886 0x8886 0x8886 0x8886 0x8886 0x8886 0x8886 0x85ca 0x85ca 0x85ca 0x85ca 0x85ca 0x85ca 0x85ca 0x85ca 0x85ca 0x85ca 0x85ca 0x85ca 0x7ef4 0x7ef4 0x7ef4 0x7ef4 0x8020 0x8020 0x8020 0x8020 0x8020 0x8020 0x8020 0x8020 0x8020 0x8020 0x8020 0x8020 0x8020 0x8020 0x8020 0x8020>; | |
| io-channels = <0x19 0x03 0x19 0x00 0x19 0x0e 0x19 0x0f 0x19 0x10>; | |
| g_QMAX_SYS_VOL_col = <0x0a>; | |
| battery0_profile_t0 = <0x00 0xa8a6 0x51e 0x23e 0xa802 0x51e 0x47c 0xa7c6 0x526 0x6ba 0xa77f 0x526 0x8f8 0xa731 0x526 0xb36 0xa6e6 0x529 0xd74 0xa671 0x52a 0xfb2 0xa5fe 0x526 0x11f0 0xa58b 0x526 0x142e 0xa519 0x522 0x166c 0xa4a6 0x526 0x18aa 0xa439 0x52d 0x1ae8 0xa3c7 0x52e 0x1d26 0xa357 0x52d 0x1f64 0xa2e4 0x52d 0x21a2 0xa278 0x52e 0x23e0 0xa20b 0x538 0x261e 0xa19f 0x53d 0x285c 0xa132 0x53c 0x2a9a 0xa0c9 0x545 0x2cd8 0xa05c 0x540 0x2f16 0x9ff9 0x54c 0x3154 0x9f90 0x550 0x3392 0x9f29 0x558 0x35d0 0x9ec6 0x563 0x380e 0x9e63 0x568 0x3a4c 0x9e00 0x56f 0x3c8a 0x9d9d 0x573 0x3ec8 0x9d40 0x57c 0x4106 0x9cdc 0x57b 0x4344 0x9c79 0x57b 0x4582 0x9c16 0x57b 0x47c0 0x9bb6 0x57b 0x49fe 0x9b4c 0x577 0x4c3c 0x9ae6 0x573 0x4e7a 0x9a7a 0x56f 0x50b8 0x9a0d 0x564 0x52f6 0x999a 0x558 0x5534 0x992b 0x549 0x5772 0x98c1 0x538 0x59b0 0x986b 0x536 0x5bee 0x9817 0x52d 0x5e2c 0x97cc 0x529 0x606a 0x9788 0x52d 0x62a8 0x9747 0x529 0x64e6 0x9709 0x531 0x6724 0x96d1 0x535 0x6962 0x9696 0x535 0x6ba0 0x9662 0x53a 0x6dde 0x962d 0x53a 0x701c 0x95f8 0x53c 0x725a 0x95ca 0x545 0x7498 0x9598 0x549 0x76d6 0x956d 0x550 0x7914 0x9541 0x558 0x7b52 0x9513 0x55d 0x7d90 0x94eb 0x564 0x7fce 0x94c2 0x567 0x820c 0x9497 0x568 0x844a 0x9475 0x56f 0x8688 0x944d 0x56f 0x88c6 0x942a 0x577 0x8b04 0x9402 0x573 0x8d42 0x93e0 0x577 0x8f80 0x93be 0x577 0x91be 0x939f 0x583 0x93fc 0x937a 0x580 0x963a 0x935b 0x58b 0x9878 0x9339 0x58f 0x9ab6 0x931a 0x59a 0x9cf4 0x92f4 0x5a1 0x9f32 0x92cf 0x5a9 0xa170 0x92a7 0x5b9 0xa3ae 0x927c 0x5c2 0xa5ec 0x9253 0x5d7 0xa82a 0x9225 0x5e7 0xaa68 0x91f0 0x5f3 0xaca6 0x91b8 0x60a 0xaee4 0x917a 0x621 0xb122 0x9136 0x631 0xb360 0x90f2 0x650 0xb59e 0x90a7 0x65f 0xb7dc 0x9063 0x67b 0xba1a 0x902b 0x69d 0xbc58 0x9006 0x6cc 0xbe96 0x8fe7 0x6fe 0xc0d4 0x8fc2 0x731 0xc312 0x8f90 0x776 0xc550 0x8f3d 0x7c1 0xc78e 0x8eb7 0x80a 0xc9cc 0x8dd2 0x841 0xcc0a 0x8c61 0x873 0xce48 0x8a58 0x8c4 0xd086 0x878c 0x943 0xd2c4 0x84aa 0x99c>; | |
| DIFFERENCE_FULLOCV_ITH = <0xfa>; | |
| battery0_profile_t4_col = <0x03>; | |
| battery0_profile_t5_num = <0x5f>; | |
| g_FG_charge_PSEUDO100_row = <0x04>; | |
| g_FG_PSEUDO100_T1 = <0x64>; | |
| battery0_profile_t2 = <0x00 0xa8a6 0x51e 0x23e 0xa802 0x51e 0x47c 0xa7c6 0x526 0x6ba 0xa77f 0x526 0x8f8 0xa731 0x526 0xb36 0xa6e6 0x529 0xd74 0xa671 0x52a 0xfb2 0xa5fe 0x526 0x11f0 0xa58b 0x526 0x142e 0xa519 0x522 0x166c 0xa4a6 0x526 0x18aa 0xa439 0x52d 0x1ae8 0xa3c7 0x52e 0x1d26 0xa357 0x52d 0x1f64 0xa2e4 0x52d 0x21a2 0xa278 0x52e 0x23e0 0xa20b 0x538 0x261e 0xa19f 0x53d 0x285c 0xa132 0x53c 0x2a9a 0xa0c9 0x545 0x2cd8 0xa05c 0x540 0x2f16 0x9ff9 0x54c 0x3154 0x9f90 0x550 0x3392 0x9f29 0x558 0x35d0 0x9ec6 0x563 0x380e 0x9e63 0x568 0x3a4c 0x9e00 0x56f 0x3c8a 0x9d9d 0x573 0x3ec8 0x9d40 0x57c 0x4106 0x9cdc 0x57b 0x4344 0x9c79 0x57b 0x4582 0x9c16 0x57b 0x47c0 0x9bb6 0x57b 0x49fe 0x9b4c 0x577 0x4c3c 0x9ae6 0x573 0x4e7a 0x9a7a 0x56f 0x50b8 0x9a0d 0x564 0x52f6 0x999a 0x558 0x5534 0x992b 0x549 0x5772 0x98c1 0x538 0x59b0 0x986b 0x536 0x5bee 0x9817 0x52d 0x5e2c 0x97cc 0x529 0x606a 0x9788 0x52d 0x62a8 0x9747 0x529 0x64e6 0x9709 0x531 0x6724 0x96d1 0x535 0x6962 0x9696 0x535 0x6ba0 0x9662 0x53a 0x6dde 0x962d 0x53a 0x701c 0x95f8 0x53c 0x725a 0x95ca 0x545 0x7498 0x9598 0x549 0x76d6 0x956d 0x550 0x7914 0x9541 0x558 0x7b52 0x9513 0x55d 0x7d90 0x94eb 0x564 0x7fce 0x94c2 0x567 0x820c 0x9497 0x568 0x844a 0x9475 0x56f 0x8688 0x944d 0x56f 0x88c6 0x942a 0x577 0x8b04 0x9402 0x573 0x8d42 0x93e0 0x577 0x8f80 0x93be 0x577 0x91be 0x939f 0x583 0x93fc 0x937a 0x580 0x963a 0x935b 0x58b 0x9878 0x9339 0x58f 0x9ab6 0x931a 0x59a 0x9cf4 0x92f4 0x5a1 0x9f32 0x92cf 0x5a9 0xa170 0x92a7 0x5b9 0xa3ae 0x927c 0x5c2 0xa5ec 0x9253 0x5d7 0xa82a 0x9225 0x5e7 0xaa68 0x91f0 0x5f3 0xaca6 0x91b8 0x60a 0xaee4 0x917a 0x621 0xb122 0x9136 0x631 0xb360 0x90f2 0x650 0xb59e 0x90a7 0x65f 0xb7dc 0x9063 0x67b 0xba1a 0x902b 0x69d 0xbc58 0x9006 0x6cc 0xbe96 0x8fe7 0x6fe 0xc0d4 0x8fc2 0x731 0xc312 0x8f90 0x776 0xc550 0x8f3d 0x7c1 0xc78e 0x8eb7 0x80a 0xc9cc 0x8dd2 0x841 0xcc0a 0x8c61 0x873 0xce48 0x8a58 0x8c4 0xd086 0x878c 0x943 0xd2c4 0x84aa 0x99c>; | |
| phandle = <0xd3>; | |
| SHUTDOWN_GAUGE0_VOLTAGE = <0x84d0>; | |
| battery0_profile_t2_num = <0x5f>; | |
| g_FG_PSEUDO100_T0 = <0x64>; | |
| MULTI_TEMP_GAUGE0 = <0x01>; | |
| COM_FG_METER_RESISTANCE = <0x64>; | |
| TEMPERATURE_T0 = <0x32>; | |
| SHUTDOWN_1_TIME = <0x05>; | |
| bootmode = <0x50>; | |
| Q_MAX_SYS_VOLTAGE_BAT3 = <0xd16>; | |
| POWERON_SYSTEM_IBOOT = <0x1f4>; | |
| g_FG_PSEUDO100_T2 = <0x64>; | |
| enable_tmp_intr_suspend = <0x00>; | |
| FG_METER_RESISTANCE = <0x46>; | |
| battery0_profile_t1 = <0x00 0xa8a6 0x51e 0x23e 0xa802 0x51e 0x47c 0xa7c6 0x526 0x6ba 0xa77f 0x526 0x8f8 0xa731 0x526 0xb36 0xa6e6 0x529 0xd74 0xa671 0x52a 0xfb2 0xa5fe 0x526 0x11f0 0xa58b 0x526 0x142e 0xa519 0x522 0x166c 0xa4a6 0x526 0x18aa 0xa439 0x52d 0x1ae8 0xa3c7 0x52e 0x1d26 0xa357 0x52d 0x1f64 0xa2e4 0x52d 0x21a2 0xa278 0x52e 0x23e0 0xa20b 0x538 0x261e 0xa19f 0x53d 0x285c 0xa132 0x53c 0x2a9a 0xa0c9 0x545 0x2cd8 0xa05c 0x540 0x2f16 0x9ff9 0x54c 0x3154 0x9f90 0x550 0x3392 0x9f29 0x558 0x35d0 0x9ec6 0x563 0x380e 0x9e63 0x568 0x3a4c 0x9e00 0x56f 0x3c8a 0x9d9d 0x573 0x3ec8 0x9d40 0x57c 0x4106 0x9cdc 0x57b 0x4344 0x9c79 0x57b 0x4582 0x9c16 0x57b 0x47c0 0x9bb6 0x57b 0x49fe 0x9b4c 0x577 0x4c3c 0x9ae6 0x573 0x4e7a 0x9a7a 0x56f 0x50b8 0x9a0d 0x564 0x52f6 0x999a 0x558 0x5534 0x992b 0x549 0x5772 0x98c1 0x538 0x59b0 0x986b 0x536 0x5bee 0x9817 0x52d 0x5e2c 0x97cc 0x529 0x606a 0x9788 0x52d 0x62a8 0x9747 0x529 0x64e6 0x9709 0x531 0x6724 0x96d1 0x535 0x6962 0x9696 0x535 0x6ba0 0x9662 0x53a 0x6dde 0x962d 0x53a 0x701c 0x95f8 0x53c 0x725a 0x95ca 0x545 0x7498 0x9598 0x549 0x76d6 0x956d 0x550 0x7914 0x9541 0x558 0x7b52 0x9513 0x55d 0x7d90 0x94eb 0x564 0x7fce 0x94c2 0x567 0x820c 0x9497 0x568 0x844a 0x9475 0x56f 0x8688 0x944d 0x56f 0x88c6 0x942a 0x577 0x8b04 0x9402 0x573 0x8d42 0x93e0 0x577 0x8f80 0x93be 0x577 0x91be 0x939f 0x583 0x93fc 0x937a 0x580 0x963a 0x935b 0x58b 0x9878 0x9339 0x58f 0x9ab6 0x931a 0x59a 0x9cf4 0x92f4 0x5a1 0x9f32 0x92cf 0x5a9 0xa170 0x92a7 0x5b9 0xa3ae 0x927c 0x5c2 0xa5ec 0x9253 0x5d7 0xa82a 0x9225 0x5e7 0xaa68 0x91f0 0x5f3 0xaca6 0x91b8 0x60a 0xaee4 0x917a 0x621 0xb122 0x9136 0x631 0xb360 0x90f2 0x650 0xb59e 0x90a7 0x65f 0xb7dc 0x9063 0x67b 0xba1a 0x902b 0x69d 0xbc58 0x9006 0x6cc 0xbe96 0x8fe7 0x6fe 0xc0d4 0x8fc2 0x731 0xc312 0x8f90 0x776 0xc550 0x8f3d 0x7c1 0xc78e 0x8eb7 0x80a 0xc9cc 0x8dd2 0x841 0xcc0a 0x8c61 0x873 0xce48 0x8a58 0x8c4 0xd086 0x878c 0x943 0xd2c4 0x84aa 0x99c>; | |
| CAR_TUNE_VALUE = <0x65>; | |
| g_PMIC_MIN_VOL_row = <0x04>; | |
| TEMPERATURE_T4 = <0xfffffff9>; | |
| battery0_profile_t2_col = <0x03>; | |
| battery0_profile_t1_col = <0x03>; | |
| g_PMIC_MIN_VOL = <0x82dc 0x82dc 0x82dc 0x82dc 0x80e8 0x80e8 0x80e8 0x80e8 0x80e8 0x80e8 0x80e8 0x80e8 0x7dc8 0x7dc8 0x7dc8 0x7dc8 0x7918 0x7918 0x7918 0x7918 0x7b0c 0x7b0c 0x7b0c 0x7b0c 0x7918 0x7918 0x7918 0x7918 0x7918 0x7918 0x7918 0x7918 0x7918 0x7918 0x7918 0x7918 0x7918 0x7918 0x7918 0x79e0>; | |
| g_FG_charge_PSEUDO100_col = <0x0a>; | |
| g_FG_PSEUDO100_col = <0x0a>; | |
| battery0_profile_t5_col = <0x03>; | |
| TEMPERATURE_T5 = <0xfffffff6>; | |
| g_PON_SYS_IBOOT = <0x1388 0x1388 0x1388 0x1388 0x1388 0x1388 0x1388 0x1388 0x1388 0x1388 0x1388 0x1388 0x1388 0x1388 0x1388 0x1388 0x1388 0x1388 0x1388 0x1388 0x1388 0x1388 0x1388 0x1388 0x1388 0x1388 0x1388 0x1388 0x1388 0x1388 0x1388 0x1388 0x1388 0x1388 0x1388 0x1388 0x1388 0x1388 0x1388 0x1388>; | |
| battery0_profile_t3 = <0x00 0xa8a6 0x51e 0x23e 0xa802 0x51e 0x47c 0xa7c6 0x526 0x6ba 0xa77f 0x526 0x8f8 0xa731 0x526 0xb36 0xa6e6 0x529 0xd74 0xa671 0x52a 0xfb2 0xa5fe 0x526 0x11f0 0xa58b 0x526 0x142e 0xa519 0x522 0x166c 0xa4a6 0x526 0x18aa 0xa439 0x52d 0x1ae8 0xa3c7 0x52e 0x1d26 0xa357 0x52d 0x1f64 0xa2e4 0x52d 0x21a2 0xa278 0x52e 0x23e0 0xa20b 0x538 0x261e 0xa19f 0x53d 0x285c 0xa132 0x53c 0x2a9a 0xa0c9 0x545 0x2cd8 0xa05c 0x540 0x2f16 0x9ff9 0x54c 0x3154 0x9f90 0x550 0x3392 0x9f29 0x558 0x35d0 0x9ec6 0x563 0x380e 0x9e63 0x568 0x3a4c 0x9e00 0x56f 0x3c8a 0x9d9d 0x573 0x3ec8 0x9d40 0x57c 0x4106 0x9cdc 0x57b 0x4344 0x9c79 0x57b 0x4582 0x9c16 0x57b 0x47c0 0x9bb6 0x57b 0x49fe 0x9b4c 0x577 0x4c3c 0x9ae6 0x573 0x4e7a 0x9a7a 0x56f 0x50b8 0x9a0d 0x564 0x52f6 0x999a 0x558 0x5534 0x992b 0x549 0x5772 0x98c1 0x538 0x59b0 0x986b 0x536 0x5bee 0x9817 0x52d 0x5e2c 0x97cc 0x529 0x606a 0x9788 0x52d 0x62a8 0x9747 0x529 0x64e6 0x9709 0x531 0x6724 0x96d1 0x535 0x6962 0x9696 0x535 0x6ba0 0x9662 0x53a 0x6dde 0x962d 0x53a 0x701c 0x95f8 0x53c 0x725a 0x95ca 0x545 0x7498 0x9598 0x549 0x76d6 0x956d 0x550 0x7914 0x9541 0x558 0x7b52 0x9513 0x55d 0x7d90 0x94eb 0x564 0x7fce 0x94c2 0x567 0x820c 0x9497 0x568 0x844a 0x9475 0x56f 0x8688 0x944d 0x56f 0x88c6 0x942a 0x577 0x8b04 0x9402 0x573 0x8d42 0x93e0 0x577 0x8f80 0x93be 0x577 0x91be 0x939f 0x583 0x93fc 0x937a 0x580 0x963a 0x935b 0x58b 0x9878 0x9339 0x58f 0x9ab6 0x931a 0x59a 0x9cf4 0x92f4 0x5a1 0x9f32 0x92cf 0x5a9 0xa170 0x92a7 0x5b9 0xa3ae 0x927c 0x5c2 0xa5ec 0x9253 0x5d7 0xa82a 0x9225 0x5e7 0xaa68 0x91f0 0x5f3 0xaca6 0x91b8 0x60a 0xaee4 0x917a 0x621 0xb122 0x9136 0x631 0xb360 0x90f2 0x650 0xb59e 0x90a7 0x65f 0xb7dc 0x9063 0x67b 0xba1a 0x902b 0x69d 0xbc58 0x9006 0x6cc 0xbe96 0x8fe7 0x6fe 0xc0d4 0x8fc2 0x731 0xc312 0x8f90 0x776 0xc550 0x8f3d 0x7c1 0xc78e 0x8eb7 0x80a 0xc9cc 0x8dd2 0x841 0xcc0a 0x8c61 0x873 0xce48 0x8a58 0x8c4 0xd086 0x878c 0x943 0xd2c4 0x84aa 0x99c>; | |
| charger = <0x53>; | |
| g_QMAX_SYS_VOL_row = <0x04>; | |
| battery0_profile_t3_col = <0x03>; | |
| g_FG_PSEUDO100_T4 = <0x64>; | |
| }; | |
| mt63xx-oc-debug { | |
| compatible = "mediatek,mt63xx-oc-debug"; | |
| }; | |
| mt6366_clock_buffer { | |
| mediatek,enable; | |
| clkbuf_ctl = <0x4e>; | |
| mediatek,clkbuf-pmic-central-base; | |
| compatible = "mediatek,clock_buffer"; | |
| mediatek,dcxo-drv-curr-support; | |
| mediatek,xo-mode-num = <0x04>; | |
| mediatek,xo-buf-support = <0x01 0x01 0x01 0x01 0x00 0x00 0x01>; | |
| phandle = <0x13f>; | |
| mediatek,xo-buf-allow-control = <0x00 0x01 0x01 0x01 0x00 0x00 0x01>; | |
| mediatek,xo-buf-name = "XO_SOC\0XO_WCN\0XO_NFC\0XO_CEL\0RSV1\0RSV2\0XO_EXT"; | |
| }; | |
| mtk_dynamic_loading_throttling { | |
| io-channel-names = "pmic_ptim\0pmic_imix_r\0pmic_batadc"; | |
| compatible = "mediatek,mt6358-dynamic_loading_throttling"; | |
| uvlo-level = <0xa28>; | |
| io-channels = <0x19 0x0f 0x19 0x10 0x19 0x00>; | |
| phandle = <0x140>; | |
| }; | |
| }; | |
| }; | |
| mtk-btcvsd-snd@18050000 { | |
| compatible = "mediatek,mtk-btcvsd-snd"; | |
| mediatek,infracfg = <0x2b>; | |
| disable_write_silence = <0x01>; | |
| reg = <0x00 0x18050000 0x00 0x1000 0x00 0x18080000 0x00 0x10000>; | |
| phandle = <0x172>; | |
| interrupts = <0x00 0x197 0x04 0x00>; | |
| mediatek,offset = <0xf00 0x800 0x140 0x144 0x148>; | |
| }; | |
| ap_ccif4@1024c000 { | |
| compatible = "mediatek,ap_ccif4"; | |
| reg = <0x00 0x1024c000 0x00 0x1000>; | |
| }; | |
| usb-phy { | |
| #size-cells = <0x02>; | |
| compatible = "mediatek,fpga-u3phy"; | |
| mediatek,ippc = <0x11f40000>; | |
| status = "disabled"; | |
| #address-cells = <0x02>; | |
| phandle = <0x199>; | |
| fpga_i2c_physical_base = <0x11eb0000>; | |
| usb-phy@0 { | |
| port = <0x00>; | |
| #phy-cells = <0x01>; | |
| phandle = <0x19a>; | |
| chip-id = <0xa60931a>; | |
| pclk_phase = <0x17>; | |
| }; | |
| }; | |
| ap_ccif0@10209000 { | |
| compatible = "mediatek,ap_ccif0"; | |
| reg = <0x00 0x10209000 0x00 0x1000>; | |
| }; | |
| audio_sram@11212000 { | |
| prefer_mode = <0x00>; | |
| compatible = "mediatek,audio_sram"; | |
| mode_size = <0x9c00 0xd000>; | |
| reg = <0x00 0x11212000 0x00 0xd000>; | |
| block_size = <0x1000>; | |
| }; | |
| masp@1000a000 { | |
| compatible = "mediatek,masp"; | |
| reg = <0x00 0x1000a000 0x00 0x1000>; | |
| phandle = <0x14e>; | |
| interrupts = <0x00 0xe6 0x04 0x00>; | |
| }; | |
| drm_wv { | |
| compatible = "mediatek,drm_wv"; | |
| status = "okay"; | |
| phandle = <0x19d>; | |
| }; | |
| opp-table0 { | |
| compatible = "operating-points-v2"; | |
| phandle = <0x8a>; | |
| opp00 { | |
| opp-hz = <0x00 0x4190ab00>; | |
| opp-microvolt = <0xdbba0>; | |
| }; | |
| opp09 { | |
| opp-hz = <0x00 0x3a2c9400>; | |
| opp-microvolt = <0xcdfe6>; | |
| }; | |
| opp18 { | |
| opp-hz = <0x00 0x3314c840>; | |
| opp-microvolt = <0xbebc2>; | |
| }; | |
| opp27 { | |
| opp-hz = <0x00 0x2d0fa500>; | |
| opp-microvolt = <0xb2872>; | |
| }; | |
| opp37 { | |
| opp-hz = <0x00 0x21f98280>; | |
| opp-microvolt = <0xa95f6>; | |
| }; | |
| opp23 { | |
| opp-hz = <0x00 0x2fbe4a40>; | |
| opp-microvolt = <0xb8a1a>; | |
| }; | |
| opp01 { | |
| opp-hz = <0x00 0x40bb0b80>; | |
| opp-microvolt = <0xda336>; | |
| }; | |
| opp28 { | |
| opp-hz = <0x00 0x2c67cc40>; | |
| opp-microvolt = <0xb1008>; | |
| }; | |
| opp30 { | |
| opp-hz = <0x00 0x2b08d880>; | |
| opp-microvolt = <0xadf34>; | |
| }; | |
| opp16 { | |
| opp-hz = <0x00 0x3473bc00>; | |
| opp-microvolt = <0xc1c96>; | |
| }; | |
| opp04 { | |
| opp-hz = <0x00 0x3e496f40>; | |
| opp-microvolt = <0xd59f8>; | |
| }; | |
| opp24 { | |
| opp-hz = <0x00 0x2f167180>; | |
| opp-microvolt = <0xb71b0>; | |
| }; | |
| opp36 { | |
| opp-hz = <0x00 0x23863d00>; | |
| opp-microvolt = <0xa95f6>; | |
| }; | |
| opp25 { | |
| opp-hz = <0x00 0x2e5f5680>; | |
| opp-microvolt = <0xb5946>; | |
| }; | |
| opp20 { | |
| opp-hz = <0x00 0x31c516c0>; | |
| opp-microvolt = <0xbbaee>; | |
| }; | |
| opp02 { | |
| opp-hz = <0x00 0x3fe56c00>; | |
| opp-microvolt = <0xd8acc>; | |
| }; | |
| opp41 { | |
| opp-hz = <0x00 0x1bd5dac0>; | |
| opp-microvolt = <0xa6522>; | |
| }; | |
| opp06 { | |
| opp-hz = <0x00 0x3c9e3040>; | |
| opp-microvolt = <0xd2924>; | |
| }; | |
| opp08 { | |
| opp-hz = <0x00 0x3b023380>; | |
| opp-microvolt = <0xcf850>; | |
| }; | |
| opp38 { | |
| opp-hz = <0x00 0x207c0a40>; | |
| opp-microvolt = <0xa7d8c>; | |
| }; | |
| opp29 { | |
| opp-hz = <0x00 0x2bb0b140>; | |
| opp-microvolt = <0xaf79e>; | |
| }; | |
| opp13 { | |
| opp-hz = <0x00 0x36e55840>; | |
| opp-microvolt = <0xc65d4>; | |
| }; | |
| opp07 { | |
| opp-hz = <0x00 0x3bc890c0>; | |
| opp-microvolt = <0xd10ba>; | |
| }; | |
| opp21 { | |
| opp-hz = <0x00 0x310dfbc0>; | |
| opp-microvolt = <0xba284>; | |
| }; | |
| opp26 { | |
| opp-hz = <0x00 0x2db77dc0>; | |
| opp-microvolt = <0xb40dc>; | |
| }; | |
| opp14 { | |
| opp-hz = <0x00 0x360fb8c0>; | |
| opp-microvolt = <0xc4d6a>; | |
| }; | |
| opp40 { | |
| opp-hz = <0x00 0x1d629540>; | |
| opp-microvolt = <0xa7d8c>; | |
| }; | |
| opp32 { | |
| opp-hz = <0x00 0x29b92700>; | |
| opp-microvolt = <0xaae60>; | |
| }; | |
| opp42 { | |
| opp-hz = <0x00 0x1a492040>; | |
| opp-microvolt = <0xa6522>; | |
| }; | |
| opp10 { | |
| opp-hz = <0x00 0x3956f480>; | |
| opp-microvolt = <0xcaf12>; | |
| }; | |
| opp44 { | |
| opp-hz = <0x00 0x173eed80>; | |
| opp-microvolt = <0xa4cb8>; | |
| }; | |
| opp34 { | |
| opp-hz = <0x00 0x269fb200>; | |
| opp-microvolt = <0xaae60>; | |
| }; | |
| opp03 { | |
| opp-hz = <0x00 0x3f0fcc80>; | |
| opp-microvolt = <0xd7262>; | |
| }; | |
| opp17 { | |
| opp-hz = <0x00 0x33bca100>; | |
| opp-microvolt = <0xc042c>; | |
| }; | |
| opp22 { | |
| opp-hz = <0x00 0x30662300>; | |
| opp-microvolt = <0xb8a1a>; | |
| }; | |
| opp31 { | |
| opp-hz = <0x00 0x2a60ffc0>; | |
| opp-microvolt = <0xac6ca>; | |
| }; | |
| opp39 { | |
| opp-hz = <0x00 0x1eef4fc0>; | |
| opp-microvolt = <0xa7d8c>; | |
| }; | |
| opp05 { | |
| opp-hz = <0x00 0x3d73cfc0>; | |
| opp-microvolt = <0xd418e>; | |
| }; | |
| opp11 { | |
| opp-hz = <0x00 0x38815500>; | |
| opp-microvolt = <0xc96a8>; | |
| }; | |
| opp33 { | |
| opp-hz = <0x00 0x282c6c80>; | |
| opp-microvolt = <0xaae60>; | |
| }; | |
| opp15 { | |
| opp-hz = <0x00 0x353a1940>; | |
| opp-microvolt = "\0\f5"; | |
| }; | |
| opp43 { | |
| opp-hz = <0x00 0x18bc65c0>; | |
| opp-microvolt = <0xa6522>; | |
| }; | |
| opp19 { | |
| opp-hz = <0x00 0x326cef80>; | |
| opp-microvolt = <0xbd358>; | |
| }; | |
| opp12 { | |
| opp-hz = <0x00 0x37baf7c0>; | |
| opp-microvolt = <0xc7e3e>; | |
| }; | |
| opp35 { | |
| opp-hz = <0x00 0x2512f780>; | |
| opp-microvolt = <0xa95f6>; | |
| }; | |
| }; | |
| emicen@10219000 { | |
| a2d_disph = <0x00>; | |
| ch_cnt = <0x02>; | |
| compatible = "mediatek,common-emicen"; | |
| reg = <0x00 0x10219000 0x00 0x1000>; | |
| phandle = <0x4c>; | |
| rk_size = <0x00 0x80000000 0x01 0x00>; | |
| a2d_hash = <0x07>; | |
| mediatek,emi-reg = <0x4b>; | |
| rk_cnt = <0x02>; | |
| }; | |
| dip_b8@15829000 { | |
| compatible = "mediatek,dip_b8"; | |
| reg = <0x00 0x15829000 0x00 0x1000>; | |
| }; | |
| md_ccif5@1025d000 { | |
| compatible = "mediatek,md_ccif5"; | |
| reg = <0x00 0x1025d000 0x00 0x1000>; | |
| }; | |
| ipe_smi_2x1_sub_comm@1b00e000 { | |
| clock-names = "apb\0smi\0gals0\0gals1"; | |
| mediatek,common-id = <0x05>; | |
| compatible = "mediatek,mt6789-smi-common\0syscon\0mediatek,smi-common\0mediatek,smi-sub-common"; | |
| mediatek,smi = <0x9e>; | |
| reg = <0x00 0x1b00e000 0x00 0x1000>; | |
| clocks = <0x2e 0x02 0x2e 0x02 0x2e 0x02 0x2e 0x02>; | |
| phandle = <0xa2>; | |
| power-domains = <0x2d 0x07>; | |
| }; | |
| mdp_tdshp0@1f00c000 { | |
| clock-names = "MDP_TDSHP0"; | |
| compatible = "mediatek,mdp_tdshp0"; | |
| reg = <0x00 0x1f00c000 0x00 0x1000>; | |
| clocks = <0x2c 0x01>; | |
| phandle = <0xb4>; | |
| }; | |
| reserved@1401f000 { | |
| compatible = "mediatek,reserved"; | |
| reg = <0x00 0x1401f000 0x00 0xe1000>; | |
| }; | |
| gpio@10005000 { | |
| gpio_init_default = <0x00 0x00 0x00 0x00 0x01 0x01 0x01 0x01 0x00 0x00 0x00 0x01 0x00 0x01 0x02 0x00 0x00 0x00 0x01 0x01 0x01 0x03 0x00 0x00 0x00 0x01 0x00 0x01 0x04 0x00 0x00 0x00 0x01 0x01 0x01 0x05 0x00 0x00 0x00 0x01 0x01 0x01 0x06 0x00 0x00 0x00 0x01 0x01 0x01 0x07 0x00 0x00 0x00 0x01 0x01 0x01 0x08 0x00 0x00 0x00 0x01 0x00 0x01 0x09 0x00 0x00 0x00 0x01 0x01 0x01 0x0a 0x00 0x00 0x00 0x01 0x01 0x01 0x0b 0x00 0x00 0x00 0x01 0x01 0x01 0x0c 0x00 0x00 0x00 0x01 0x01 0x01 0x0d 0x00 0x00 0x00 0x01 0x01 0x01 0x0e 0x06 0x00 0x00 0x01 0x00 0x00 0x0f 0x00 0x01 0x00 0x01 0x00 0x00 0x10 0x00 0x01 0x00 0x01 0x00 0x00 0x11 0x00 0x00 0x00 0x01 0x00 0x00 0x12 0x00 0x01 0x00 0x01 0x00 0x00 0x13 0x00 0x01 0x00 0x01 0x00 0x00 0x14 0x00 0x01 0x00 0x01 0x00 0x00 0x15 0x00 0x01 0x00 0x01 0x00 0x00 0x16 0x00 0x01 0x00 0x01 0x00 0x00 0x17 0x01 0x00 0x00 0x00 0x00 0x00 0x18 0x01 0x00 0x00 0x01 0x01 0x00 0x19 0x02 0x00 0x00 0x01 0x00 0x01 0x1a 0x00 0x00 0x00 0x01 0x01 0x01 0x1b 0x00 0x00 0x00 0x01 0x01 0x01 0x1c 0x01 0x00 0x00 0x01 0x01 0x01 0x1d 0x01 0x00 0x00 0x00 0x00 0x01 0x1e 0x01 0x00 0x00 0x00 0x00 0x01 0x1f 0x01 0x00 0x00 0x00 0x00 0x01 0x20 0x01 0x00 0x00 0x00 0x00 0x01 0x21 0x03 0x00 0x00 0x00 0x00 0x01 0x22 0x06 0x00 0x00 0x01 0x00 0x00 0x23 0x06 0x00 0x00 0x01 0x00 0x00 0x24 0x06 0x00 0x00 0x00 0x00 0x00 0x25 0x06 0x00 0x00 0x01 0x00 0x00 0x26 0x02 0x00 0x00 0x00 0x00 0x01 0x27 0x02 0x00 0x00 0x00 0x00 0x01 0x28 0x02 0x00 0x00 0x00 0x00 0x01 0x29 0x02 0x00 0x00 0x01 0x00 0x01 0x2a 0x00 0x00 0x00 0x01 0x01 0x00 0x2b 0x00 0x00 0x00 0x01 0x01 0x01 0x2c 0x00 0x00 0x00 0x01 0x01 0x01 0x2d 0x00 0x00 0x00 0x01 0x01 0x01 0x2e 0x00 0x00 0x00 0x01 0x01 0x01 0x2f 0x00 0x00 0x00 0x01 0x01 0x01 0x30 0x00 0x00 0x00 0x01 0x01 0x01 0x31 0x00 0x00 0x00 0x01 0x01 0x01 0x32 0x00 0x00 0x00 0x01 0x01 0x01 0x33 0x00 0x00 0x00 0x01 0x01 0x01 0x34 0x00 0x00 0x00 0x01 0x01 0x01 0x35 0x00 0x00 0x00 0x01 0x01 0x01 0x42 0x01 0x00 0x00 0x01 0x01 0x01 0x43 0x01 0x00 0x00 0x01 0x01 0x01 0x44 0x00 0x00 0x00 0x01 0x00 0x01 0x45 0x00 0x00 0x00 0x01 0x01 0x01 0x4d 0x01 0x00 0x00 0x00 0x00 0x01 0x4e 0x01 0x00 0x00 0x00 0x00 0x01 0x4f 0x01 0x00 0x00 0x01 0x01 0x01 0x50 0x01 0x00 0x00 0x00 0x00 0x01 0x51 0x01 0x00 0x00 0x00 0x00 0x01 0x52 0x01 0x00 0x00 0x01 0x01 0x01 0x53 0x01 0x00 0x00 0x01 0x00 0x01 0x54 0x01 0x00 0x00 0x00 0x00 0x01 0x55 0x01 0x00 0x00 0x00 0x00 0x01 0x56 0x00 0x01 0x00 0x01 0x00 0x00 0x57 0x00 0x01 0x00 0x01 0x00 0x00 0x58 0x00 0x01 0x00 0x01 0x00 0x00 0x59 0x01 0x00 0x00 0x01 0x00 0x00 0x5a 0x01 0x00 0x00 0x01 0x00 0x00 0x5b 0x01 0x00 0x00 0x01 0x00 0x00 0x5c 0x01 0x00 0x00 0x01 0x00 0x00 0x5d 0x01 0x00 0x00 0x01 0x00 0x00 0x5e 0x01 0x00 0x00 0x01 0x00 0x00 0x5f 0x01 0x00 0x00 0x01 0x00 0x00 0x60 0x01 0x00 0x00 0x01 0x00 0x00 0x61 0x01 0x00 0x00 0x01 0x00 0x00 0x62 0x01 0x00 0x00 0x01 0x00 0x00 0x63 0x01 0x00 0x00 0x01 0x00 0x00 0x64 0x00 0x00 0x00 0x01 0x00 0x00 0x65 0x00 0x00 0x00 0x01 0x00 0x00 0x66 0x01 0x00 0x00 0x01 0x00 0x00 0x67 0x02 0x00 0x00 0x01 0x00 0x00 0x68 0x02 0x00 0x00 0x00 0x00 0x00 0x69 0x01 0x00 0x00 0x01 0x00 0x00 0x6a 0x01 0x00 0x00 0x01 0x00 0x00 0x6b 0x01 0x00 0x00 0x01 0x00 0x00 0x6c 0x01 0x00 0x00 0x01 0x00 0x00 0x6d 0x01 0x00 0x00 0x01 0x00 0x00 0x6e 0x01 0x00 0x00 0x01 0x00 0x00 0x6f 0x00 0x00 0x00 0x00 0x00 0x00 0x70 0x01 0x00 0x00 0x00 0x00 0x00 0x71 0x01 0x00 0x00 0x01 0x00 0x00 0x72 0x01 0x00 0x00 0x00 0x00 0x00 0x73 0x01 0x00 0x00 0x01 0x00 0x00 0x74 0x01 0x00 0x00 0x00 0x00 0x00 0x75 0x01 0x00 0x00 0x01 0x00 0x00 0x76 0x01 0x00 0x00 0x00 0x00 0x00 0x77 0x01 0x00 0x00 0x01 0x00 0x00 0x78 0x01 0x00 0x00 0x00 0x00 0x00 0x79 0x01 0x00 0x00 0x01 0x00 0x00 0x7a 0x01 0x00 0x00 0x00 0x00 0x00 0x7b 0x01 0x00 0x00 0x00 0x00 0x00 0x7c 0x01 0x00 0x00 0x01 0x00 0x00 0x7d 0x01 0x00 0x00 0x01 0x00 0x00 0x7e 0x01 0x00 0x00 0x01 0x00 0x00 0x7f 0x01 0x00 0x00 0x01 0x00 0x00 0x80 0x01 0x00 0x00 0x01 0x00 0x00 0x81 0x01 0x00 0x00 0x01 0x00 0x00 0x82 0x01 0x00 0x00 0x01 0x01 0x01 0x83 0x01 0x00 0x00 0x01 0x01 0x01 0x84 0x02 0x00 0x00 0x01 0x01 0x00 0x85 0x02 0x00 0x00 0x01 0x01 0x00 0x86 0x01 0x00 0x00 0x01 0x01 0x01 0x87 0x01 0x00 0x00 0x01 0x01 0x01 0x88 0x01 0x00 0x00 0x01 0x01 0x01 0x89 0x01 0x00 0x00 0x01 0x01 0x01 0x8a 0x01 0x00 0x00 0x01 0x01 0x01 0x8b 0x01 0x00 0x00 0x01 0x01 0x01 0x8c 0x01 0x00 0x00 0x01 0x01 0x01 0x8d 0x01 0x00 0x00 0x01 0x01 0x01 0x8e 0x01 0x00 0x00 0x01 0x01 0x01 0x8f 0x01 0x00 0x00 0x01 0x01 0x01 0x90 0x01 0x00 0x00 0x01 0x01 0x01 0x91 0x01 0x00 0x00 0x01 0x01 0x01 0x92 0x01 0x00 0x00 0x01 0x01 0x01 0x93 0x01 0x00 0x00 0x01 0x01 0x01 0x94 0x02 0x00 0x00 0x01 0x01 0x01 0x95 0x02 0x00 0x00 0x01 0x01 0x01 0x96 0x00 0x01 0x00 0x01 0x00 0x01 0x97 0x00 0x01 0x00 0x01 0x00 0x01 0x98 0x00 0x01 0x00 0x01 0x00 0x01 0x99 0x00 0x01 0x01 0x01 0x00 0x01 0x9a 0x00 0x01 0x00 0x01 0x00 0x01 0x9b 0x00 0x01 0x00 0x01 0x00 0x01 0x9c 0x00 0x01 0x01 0x01 0x00 0x01 0x9d 0x00 0x01 0x00 0x01 0x00 0x01 0x9e 0x06 0x00 0x00 0x01 0x00 0x01 0x9f 0x06 0x00 0x00 0x01 0x00 0x01 0xa0 0x01 0x00 0x00 0x00 0x00 0x01 0xa1 0x01 0x00 0x00 0x00 0x00 0x01 0xa2 0x01 0x00 0x00 0x00 0x00 0x01 0xa3 0x01 0x00 0x00 0x01 0x00 0x01 0xa4 0x01 0x00 0x00 0x00 0x00 0x01 0xa5 0x01 0x00 0x00 0x00 0x00 0x01 0xa6 0x01 0x00 0x00 0x00 0x00 0x01 0xa7 0x01 0x00 0x00 0x01 0x00 0x01 0xa8 0x01 0x00 0x00 0x00 0x00 0x00 0xa9 0x01 0x00 0x00 0x00 0x00 0x01 0xaa 0x01 0x00 0x00 0x00 0x00 0x01 0xab 0x01 0x00 0x00 0x00 0x00 0x01 0xac 0x01 0x00 0x00 0x00 0x00 0x01 0xad 0x01 0x00 0x00 0x01 0x00 0x01 0xae 0x01 0x00 0x00 0x01 0x00 0x01 0xaf 0x01 0x00 0x00 0x01 0x00 0x01 0xb0 0x01 0x00 0x00 0x01 0x00 0x01 0xb1 0x00 0x00 0x00 0x01 0x00 0x00 0xb2 0x00 0x00 0x00 0x01 0x00 0x00 0xb3 0x00 0x00 0x00 0x01 0x00 0x00 0xb4 0x00 0x00 0x00 0x01 0x00 0x00 0xb5 0x00 0x00 0x00 0x01 0x00 0x00 0xb6 0x00 0x00 0x00 0x01 0x00 0x00 0xb7 0x00 0x00 0x00 0x01 0x00 0x00 0xb8 0x00 0x00 0x00 0x01 0x00 0x00 0xb9 0x00 0x00 0x00 0x01 0x00 0x00 0xba 0x01 0x00 0x00 0x01 0x01 0x01 0xbb 0x01 0x00 0x00 0x01 0x01 0x01 0xbc 0x00 0x00 0x00 0x01 0x00 0x00 0xbd 0x00 0x00 0x00 0x01 0x00 0x00 0xbe 0x00 0x00 0x00 0x01 0x00 0x00 0xbf 0x00 0x00 0x00 0x01 0x00 0x00 0xc0 0x00 0x00 0x00 0x01 0x00 0x00 0xc1 0x00 0x00 0x00 0x01 0x00 0x00 0xc2 0x00 0x00 0x00 0x01 0x00 0x00 0xc3 0x00 0x00 0x00 0x01 0x00 0x00 0xc4 0x00 0x00 0x00 0x01 0x00 0x00 0xc5 0x00 0x00 0x00 0x01 0x00 0x00 0xc6 0x00 0x00 0x00 0x01 0x00 0x00 0xc7 0x00 0x00 0x00 0x01 0x00 0x00 0xc8 0x00 0x00 0x00 0x01 0x00 0x00 0xc9 0x00 0x00 0x00 0x01 0x00 0x00 0xca 0x00 0x00 0x00 0x01 0x00 0x00 0xcb 0x00 0x00 0x00 0x01 0x00 0x00 0xcc 0x00 0x00 0x00 0x01 0x00 0x00 0xcd 0x00 0x00 0x00 0x01 0x00 0x00 0xce 0x00 0x00 0x00 0x01 0x00 0x00 0xcf 0x00 0x00 0x00 0x01 0x00 0x00 0xd0 0x00 0x00 0x00 0x01 0x00 0x00 0xd1 0x00 0x00 0x00 0x01 0x00 0x00 0xd2 0x00 0x00 0x00 0x01 0x00 0x00 0xd3 0x00 0x00 0x00 0x01 0x00 0x00 0xd4 0x00 0x00 0x00 0x01 0x00 0x00 0xd5 0x00 0x00 0x00 0x01 0x00 0x00 0xd6 0x00 0x00 0x00 0x01 0x00 0x00 0xd7 0x00 0x00 0x00 0x01 0x00 0x00 0xd8 0x00 0x00 0x00 0x01 0x00 0x00 0xd9 0x00 0x00 0x00 0x01 0x00 0x00 0xda 0x00 0x00 0x00 0x01 0x00 0x00 0xdb 0x00 0x00 0x00 0x01 0x00 0x00 0xdc 0x00 0x00 0x00 0x01 0x00 0x00 0xdd 0x00 0x00 0x00 0x01 0x00 0x00>; | |
| compatible = "mediatek,gpio"; | |
| reg = <0x00 0x10005000 0x00 0x1000>; | |
| phandle = <0x116>; | |
| }; | |
| systimer@10017000 { | |
| compatible = "mediatek,mt6789-timer\0mediatek,mt6765-timer"; | |
| reg = <0x00 0x10017000 0x00 0x1000>; | |
| clocks = <0x5f>; | |
| phandle = <0x14f>; | |
| interrupts = <0x00 0x109 0x04 0x00>; | |
| }; | |
| dramc@10230000 { | |
| freq_step = <0x10aa 0xc80 0x960 0x74a 0x640 0x4b0 0x320>; | |
| mr = <0x00 0x00 0x42b8 0x700f 0x3a88 0xc272 0x01 0x00>; | |
| fmeter_version = <0x01>; | |
| crystal_freq = <0x34>; | |
| ch_cnt = <0x02>; | |
| shu_lv = <0x50c 0x30000 0x10>; | |
| dqopen = <0x870 0x200000 0x15 0x870 0x200000 0x15>; | |
| posdiv = <0x708 0x07 0x00 0x728 0x07 0x00>; | |
| compatible = "mediatek,mt6789-dramc\0mediatek,common-dramc"; | |
| mr4_rg = <0x90 0xffff 0x00>; | |
| fbksel = <0x70c 0x40 0x06 0x70c 0x40 0x06>; | |
| cldiv2 = <0x8b4 0x02 0x01 0x8b4 0x02 0x01>; | |
| prediv = <0x708 0xc0000 0x12 0x728 0xc0000 0x12>; | |
| sdmpcw = <0x704 0xffff0000 0x10 0x724 0xffff0000 0x10>; | |
| dqsopen = <0x870 0x100000 0x14 0x870 0x100000 0x14>; | |
| pll_md = <0x744 0x100 0x08 0x744 0x100 0x08>; | |
| reg = <0x00 0x10230000 0x00 0x2000 0x00 0x10240000 0x00 0x2000 0x00 0x10234000 0x00 0x1000 0x00 0x10244000 0x00 0x1000 0x00 0x10238000 0x00 0x2000 0x00 0x10248000 0x00 0x2000 0x00 0x10236000 0x00 0x1000 0x00 0x10246000 0x00 0x1000 0x00 0x10006000 0x00 0x1000>; | |
| mr_cnt = <0x04>; | |
| ckdiv4_ca = <0xb74 0x04 0x02 0xb74 0x04 0x02>; | |
| phandle = <0x16f>; | |
| rk_size = <0x10 0x20>; | |
| dram_type = <0x06>; | |
| shu_of = <0x700>; | |
| support_ch_cnt = <0x02>; | |
| pll_id = <0x50c 0x100 0x08>; | |
| mr4_version = <0x01>; | |
| ckdiv4 = <0x874 0x04 0x02 0x874 0x04 0x02>; | |
| freq_cnt = <0x07>; | |
| rk_cnt = <0x02>; | |
| }; | |
| md_ccif2@1023d000 { | |
| compatible = "mediatek,md_ccif2"; | |
| reg = <0x00 0x1023d000 0x00 0x1000>; | |
| }; | |
| spi2@11012000 { | |
| clock-names = "parent-clk\0sel-clk\0spi-clk"; | |
| compatible = "mediatek,mt6789-spi"; | |
| mediatek,pad-select = <0x00>; | |
| reg = <0x00 0x11012000 0x00 0x100>; | |
| clocks = <0x2a 0x7f 0x2a 0x12 0x2b 0x27>; | |
| phandle = <0x154>; | |
| interrupts = <0x00 0xc1 0x04 0x00>; | |
| }; | |
| infra_mbist@1020d000 { | |
| compatible = "mediatek,infra_mbist"; | |
| reg = <0x00 0x1020d000 0x00 0x1000>; | |
| }; | |
| i2c@11f00000 { | |
| clock-names = "main\0dma"; | |
| clock-div = <0x01>; | |
| compatible = "mediatek,mt6983-i2c"; | |
| reg = <0x00 0x11f00000 0x00 0x1000 0x00 0x10217500 0x00 0x80>; | |
| clocks = <0x36 0x00 0x2b 0x3d>; | |
| phandle = <0x16c>; | |
| interrupts = <0x00 0x97 0x04 0x00>; | |
| HL7138@55 { | |
| compatible = "Halomicro,HL7138"; | |
| status = "okay"; | |
| HL7138,intr-gpios = <0x49 0x05 0x00>; | |
| reg = <0x55>; | |
| phandle = <0x1fa>; | |
| }; | |
| }; | |
| dramc_ch1_rsv@10900000 { | |
| compatible = "mediatek,dramc_ch1_rsv"; | |
| reg = <0x00 0x10900000 0x00 0x40000>; | |
| }; | |
| disp_color0@14009000 { | |
| compatible = "mediatek,disp_color0\0mediatek,mt6789-disp-color"; | |
| reg = <0x00 0x14009000 0x00 0x1000>; | |
| clocks = <0x35 0x09>; | |
| phandle = <0x184>; | |
| interrupts = <0x00 0x123 0x04 0x00>; | |
| }; | |
| dip_b4@15825000 { | |
| compatible = "mediatek,dip_b4"; | |
| reg = <0x00 0x15825000 0x00 0x1000>; | |
| }; | |
| dispsys_config@14000000 { | |
| iommus = <0x43 0x21>; | |
| clock-num = <0x03>; | |
| operating-points-v2 = <0x47>; | |
| mediatek,larb = <0x94>; | |
| gce-subsys = <0x66 0x14000000 0x01 0x66 0x14010000 0x02 0x66 0x14020000 0x03>; | |
| helper-name = "MTK_DRM_OPT_STAGE\0MTK_DRM_OPT_USE_CMDQ\0MTK_DRM_OPT_USE_M4U\0MTK_DRM_OPT_MMQOS_SUPPORT\0MTK_DRM_OPT_MMDVFS_SUPPORT\0MTK_DRM_OPT_SODI_SUPPORT\0MTK_DRM_OPT_IDLE_MGR\0MTK_DRM_OPT_IDLEMGR_SWTCH_DECOUPLE\0MTK_DRM_OPT_IDLEMGR_BY_REPAINT\0MTK_DRM_OPT_IDLEMGR_ENTER_ULPS\0MTK_DRM_OPT_IDLEMGR_KEEP_LP11\0MTK_DRM_OPT_DYNAMIC_RDMA_GOLDEN_SETTING\0MTK_DRM_OPT_IDLEMGR_DISABLE_ROUTINE_IRQ\0MTK_DRM_OPT_MET_LOG\0MTK_DRM_OPT_USE_PQ\0MTK_DRM_OPT_ESD_CHECK_RECOVERY\0MTK_DRM_OPT_ESD_CHECK_SWITCH\0MTK_DRM_OPT_PRESENT_FENCE\0MTK_DRM_OPT_RDMA_UNDERFLOW_AEE\0MTK_DRM_OPT_DSI_UNDERRUN_AEE\0MTK_DRM_OPT_HRT\0MTK_DRM_OPT_HRT_MODE\0MTK_DRM_OPT_DELAYED_TRIGGER\0MTK_DRM_OPT_OVL_EXT_LAYER\0MTK_DRM_OPT_AOD\0MTK_DRM_OPT_RPO\0MTK_DRM_OPT_DUAL_PIPE\0MTK_DRM_OPT_DC_BY_HRT\0MTK_DRM_OPT_OVL_WCG\0MTK_DRM_OPT_OVL_SBCH\0MTK_DRM_OPT_COMMIT_NO_WAIT_VBLANK\0MTK_DRM_OPT_MET\0MTK_DRM_OPT_REG_PARSER_RAW_DUMP\0MTK_DRM_OPT_VP_PQ\0MTK_DRM_OPT_GAME_PQ\0MTK_DRM_OPT_MMPATH\0MTK_DRM_OPT_HBM\0MTK_DRM_OPT_VDS_PATH_SWITCH\0MTK_DRM_OPT_LAYER_REC\0MTK_DRM_OPT_CLEAR_LAYER\0MTK_DRM_OPT_LFR\0MTK_DRM_OPT_SF_PF\0MTK_DRM_OPT_DYN_MIPI_CHANGE\0MTK_DRM_OPT_PRIM_DUAL_PIPE\0MTK_DRM_OPT_MSYNC2_0\0MTK_DRM_OPT_VIRTUAL_DISP\0MTK_DRM_OPT_MML_PRIMARY"; | |
| compatible = "mediatek,mt6789-disp"; | |
| mboxes = <0x66 0x00 0x00 0x04 0x66 0x01 0x00 0x04 0x66 0x02 0x00 0x04 0x66 0x03 0xffffffff 0x02 0x66 0x04 0x00 0x04 0x66 0x06 0x00 0x03>; | |
| pinctrl-1 = <0x1d0>; | |
| pinctrl-names = "lcm_rst_out1_gpio\0lcm_rst_out0_gpio\0mode_te_te"; | |
| status = "okay"; | |
| fake-engine = <0x93 0x03 0x94 0x24>; | |
| pinctrl-2 = <0x1d1>; | |
| interconnect-names = "disp_hrt_qos"; | |
| gce-events = <0x66 0x1b2 0x66 0x280 0x66 0x1c2 0x66 0x281 0x66 0x19a 0x66 0x282 0x66 0x19e 0x66 0x19b 0x66 0x283 0x66 0x284 0x66 0x19b 0x66 0x18e 0x66 0x2b4 0x66 0x2b5 0x66 0x2b4 0x66 0x2b5>; | |
| mediatek,smi-id = <0x01>; | |
| reg = <0x00 0x14000000 0x00 0x1000>; | |
| dvfsrc-vcore-supply = <0x42>; | |
| gce-event-names = "disp_mutex0_eof\0disp_token_stream_dirty0\0disp_wait_dsi0_te\0disp_token_stream_eof0\0disp_dsi0_eof\0disp_token_esd_eof0\0disp_rdma0_eof0\0disp_wdma0_eof0\0disp_token_stream_block0\0disp_token_cabc_eof0\0disp_wdma0_eof2\0disp_dsi0_sof0\0disp_token_disp_va_start0\0disp_token_disp_va_end0\0disp_token_disp_va_start2\0disp_token_disp_va_end2"; | |
| clocks = <0x35 0x16 0x35 0x01 0x35 0x00>; | |
| phandle = <0x67>; | |
| interconnects = <0xa3 0x30017 0xa3 0x10000>; | |
| mediatek,mailbox-gce = <0x66>; | |
| helper-value = <0x00 0x01 0x01 0x01 0x01 0x00 0x01 0x00 0x01 0x00 0x00 0x00 0x01 0x00 0x01 0x01 0x01 0x01 0x00 0x01 0x01 0x01 0x00 0x01 0x00 0x01 0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x00 0x01 0x00 0x00 0x00 0x00>; | |
| gce-client-names = "CLIENT_CFG0\0CLIENT_CFG1\0CLIENT_CFG2\0CLIENT_TRIG_LOOP0\0CLIENT_SUB_CFG0\0CLIENT_DSI_CFG0"; | |
| #clock-cells = <0x01>; | |
| pinctrl-0 = <0x1cf>; | |
| power-domains = <0x2d 0x0a>; | |
| }; | |
| dip_b5@15826000 { | |
| compatible = "mediatek,dip_b5"; | |
| reg = <0x00 0x15826000 0x00 0x1000>; | |
| }; | |
| mss_b@15812000 { | |
| compatible = "mediatek,mss_b"; | |
| reg = <0x00 0x15812000 0x00 0x1000>; | |
| }; | |
| dip_b6@15827000 { | |
| compatible = "mediatek,dip_b6"; | |
| reg = <0x00 0x15827000 0x00 0x1000>; | |
| }; | |
| i2c@11eb3000 { | |
| clock-names = "main\0dma"; | |
| clock-div = <0x01>; | |
| compatible = "mediatek,mt6983-i2c"; | |
| reg = <0x00 0x11eb3000 0x00 0x1000 0x00 0x10217700 0x00 0x80>; | |
| clocks = <0x37 0x03 0x2b 0x3d>; | |
| phandle = <0x16e>; | |
| interrupts = <0x00 0x99 0x04 0x00>; | |
| }; | |
| devapc_ao_infra_peri@10023000 { | |
| compatible = "mediatek,devapc_ao_infra_peri"; | |
| reg = <0x00 0x10023000 0x00 0x1000>; | |
| }; | |
| seninf6@1a009000 { | |
| compatible = "mediatek,seninf6"; | |
| reg = <0x00 0x1a009000 0x00 0x1000>; | |
| }; | |
| btif@1100c000 { | |
| clock-names = "btifc\0apdmac"; | |
| compatible = "mediatek,btif"; | |
| reg = <0x00 0x1100c000 0x00 0x1000 0x00 0x10217b00 0x00 0x80 0x00 0x10217b80 0x00 0x80>; | |
| clocks = <0x2b 0x12 0x2b 0x3d>; | |
| phandle = <0xd2>; | |
| interrupts = <0x00 0xbe 0x04 0x00 0x00 0xb8 0x04 0x00 0x00 0xb9 0x04 0x00>; | |
| }; | |
| mmc@11230000 { | |
| clock-names = "bus_clk\0source\0crypto_clk\0hclk\0source_cg\0crypto_cg"; | |
| mmc-hs400-1_8v; | |
| hs400-ds-delay = <0x12814>; | |
| non-removable; | |
| mmc-ddr-1_8v; | |
| bus-width = <0x08>; | |
| cap-mmc-highspeed; | |
| ocr-voltage = <0x30000>; | |
| compatible = "mediatek,mt6789-mmc"; | |
| max-frequency = <0xbebc200>; | |
| req-vcore = <0x9eb10>; | |
| pinctrl-1 = <0x83>; | |
| no-sdio; | |
| pinctrl-names = "default\0state_uhs\0pull_down"; | |
| status = "disabled"; | |
| pinctrl-2 = <0x84>; | |
| reg = <0x00 0x11230000 0x00 0x10000 0x00 0x11f50000 0x00 0x1000>; | |
| dvfsrc-vcore-supply = <0x42>; | |
| clocks = <0x2a 0x13 0x2a 0x14 0x2a 0x32 0x2b 0x14 0x2b 0x16 0x2b 0x1d>; | |
| phandle = <0x177>; | |
| vmmc-supply = <0x81>; | |
| mmc-hs200-1_8v; | |
| supports-cqe; | |
| no-sd; | |
| pinctrl-0 = <0x82>; | |
| interrupts = <0x00 0x83 0x04 0x00>; | |
| host-index = <0x00>; | |
| }; | |
| smi_larb14@1a002000 { | |
| clock-names = "apb\0smi"; | |
| compatible = "mediatek,smi_larb14\0mediatek,mt6789-smi-larb\0mediatek,smi-larb"; | |
| mediatek,smi = <0x9f>; | |
| mediatek,larb-id = <0x0e>; | |
| reg = <0x00 0x1a002000 0x00 0x1000>; | |
| clocks = <0x31 0x01 0x31 0x01>; | |
| phandle = <0x99>; | |
| power-domains = <0x2d 0x0c>; | |
| }; | |
| smi_larb20@1b00f000 { | |
| clock-names = "apb\0smi"; | |
| compatible = "mediatek,smi_larb20\0mediatek,mt6789-smi-larb\0mediatek,smi-larb"; | |
| mediatek,smi = <0xa2>; | |
| mediatek,larb-id = <0x14>; | |
| reg = <0x00 0x1b00f000 0x00 0x1000>; | |
| clocks = <0x2e 0x01 0x2e 0x01>; | |
| phandle = <0x9a>; | |
| power-domains = <0x2d 0x07>; | |
| }; | |
| mm_vpu_m1_sub_common@1030c000 { | |
| compatible = "mediatek,mm_vpu_m1_sub_common"; | |
| reg = <0x00 0x1030c000 0x00 0x1000>; | |
| }; | |
| dma-controller@10217800 { | |
| clock-names = "apdma"; | |
| #dma-cells = <0x01>; | |
| compatible = "mediatek,mt6779-uart-dma"; | |
| dma-requests = <0x04>; | |
| reg = <0x00 0x10217800 0x00 0x80 0x00 0x10217880 0x00 0x80 0x00 0x10217900 0x00 0x80 0x00 0x10217980 0x00 0x80>; | |
| clocks = <0x2b 0x3d>; | |
| phandle = <0x60>; | |
| interrupts = <0x00 0xb2 0x04 0x00 0x00 0xb3 0x04 0x00 0x00 0xb4 0x04 0x00 0x00 0xb5 0x04 0x00>; | |
| }; | |
| disp_ovl0@14005000 { | |
| iommus = <0x43 0x02 0x43 0x01>; | |
| mediatek,larb = <0x93>; | |
| compatible = "mediatek,disp_ovl0\0mediatek,mt6789-disp-ovl"; | |
| interconnect-names = "DDP_COMPONENT_OVL0_qos\0DDP_COMPONENT_OVL0_fbdc_qos\0DDP_COMPONENT_OVL0_hrt_qos"; | |
| mediatek,smi-id = <0x00>; | |
| reg = <0x00 0x14005000 0x00 0x1000>; | |
| clocks = <0x35 0x02>; | |
| phandle = <0x180>; | |
| interconnects = <0xa3 0x40002 0xa3 0x10000 0xa3 0x40002 0xa3 0x10000 0xa3 0x40002 0xa3 0x10000>; | |
| interrupts = <0x00 0x11f 0x04 0x00>; | |
| }; | |
| dip_b7@15828000 { | |
| compatible = "mediatek,dip_b7"; | |
| reg = <0x00 0x15828000 0x00 0x1000>; | |
| }; | |
| mdp_rsz0@1f008000 { | |
| clock-names = "MDP_RSZ0"; | |
| compatible = "mediatek,mdp_rsz0"; | |
| reg = <0x00 0x1f008000 0x00 0x1000>; | |
| clocks = <0x2c 0x07>; | |
| phandle = <0xb0>; | |
| }; | |
| mali@13000000 { | |
| operating-points-v2 = <0x8a>; | |
| compatible = "mediatek,mali\0arm,mali-valhall"; | |
| #cooling-cells = <0x02>; | |
| reg = <0x00 0x13000000 0x00 0x4000>; | |
| phandle = <0x1d>; | |
| interrupt-names = "GPU\0MMU\0JOB\0EVENT\0PWR"; | |
| ged-supply = <0x8b>; | |
| interrupts = <0x00 0x18c 0x04 0x00 0x00 0x18d 0x04 0x00 0x00 0x18e 0x04 0x00 0x00 0x18f 0x04 0x00 0x00 0x190 0x04 0x00>; | |
| }; | |
| sys_cirq@10314000 { | |
| compatible = "mediatek,sys_cirq"; | |
| reg = <0x00 0x10314000 0x00 0x1000>; | |
| }; | |
| pinctrl { | |
| gpio-controller; | |
| compatible = "mediatek,mt6789-pinctrl"; | |
| #gpio-cells = <0x02>; | |
| #interrupt-cells = <0x02>; | |
| reg = <0x00 0x10005000 0x00 0x1000 0x00 0x11c30000 0x00 0x1000 0x00 0x11d10000 0x00 0x1000 0x00 0x11d40000 0x00 0x1000 0x00 0x11e20000 0x00 0x1000 0x00 0x11e60000 0x00 0x1000 0x00 0x11ea0000 0x00 0x1000>; | |
| phandle = <0x49>; | |
| mediatek,eint = <0x4a>; | |
| interrupt-controller; | |
| gpio-ranges = <0x49 0x00 0x00 0xbc>; | |
| reg-names = "gpio\0iocfg_rb\0iocfg_bm\0iocfg_br\0iocfg_lm\0iocfg_bl\0iocfg_rt"; | |
| lcm_led_en1_gpio { | |
| phandle = <0x1cd>; | |
| pins_cmd_dat { | |
| slew-rate = <0x01>; | |
| output-high; | |
| pinmux = <0x9a00>; | |
| }; | |
| }; | |
| hwen_high { | |
| phandle = <0x1e8>; | |
| pins_cmd_dat { | |
| slew-rate = <0x01>; | |
| output-high; | |
| pinmux = <0x9d00>; | |
| }; | |
| }; | |
| cam2@1 { | |
| phandle = <0x1ba>; | |
| pins_cmd_dat { | |
| slew-rate = <0x01>; | |
| output-high; | |
| pinmux = <0x1600>; | |
| }; | |
| }; | |
| int_suspend { | |
| phandle = <0x1de>; | |
| pins_cmd_dat { | |
| output-low; | |
| pinmux = <0x900>; | |
| }; | |
| }; | |
| cam0@0 { | |
| phandle = <0x1b5>; | |
| pins_cmd_dat { | |
| output-low; | |
| slew-rate = <0x01>; | |
| pinmux = <0x1400>; | |
| }; | |
| }; | |
| aud_clk_miso_off { | |
| phandle = <0x6c>; | |
| pins_cmd0_dat { | |
| bias-pull-down; | |
| pinmux = <0xad00>; | |
| input-enable; | |
| }; | |
| }; | |
| cam1@0 { | |
| phandle = <0x1b7>; | |
| pins_cmd_dat { | |
| output-low; | |
| slew-rate = <0x01>; | |
| pinmux = <0x1000>; | |
| }; | |
| }; | |
| camera_pins_cam0_mclk_4ma { | |
| phandle = <0x1bd>; | |
| pins_cmd_dat { | |
| drive-strength = <0x01>; | |
| pinmux = <0x8001>; | |
| }; | |
| }; | |
| fan_control_set_on { | |
| phandle = <0x1ef>; | |
| pins_cmd0_dat { | |
| slew-rate = <0x01>; | |
| output-high; | |
| pinmux = <0x2103>; | |
| }; | |
| pins_cmd1_dat { | |
| slew-rate = <0x01>; | |
| output-high; | |
| pinmux = <0x9700>; | |
| }; | |
| }; | |
| mmc1@0 { | |
| phandle = <0x86>; | |
| pins_clk { | |
| drive-strength = <0x03>; | |
| bias-pull-down = <0x66>; | |
| pinmux = <0x4701>; | |
| }; | |
| pins_cmd_dat { | |
| drive-strength = <0x03>; | |
| pinmux = <0x4901 0x4a01 0x4b01 0x4c01 0x4801>; | |
| bias-pull-up = <0x65>; | |
| input-enable; | |
| }; | |
| }; | |
| reset_suspend { | |
| phandle = <0x1df>; | |
| pins_cmd_dat { | |
| output-low; | |
| pinmux = <0x9800>; | |
| }; | |
| }; | |
| reset_active { | |
| phandle = <0x1dd>; | |
| pins_cmd_dat { | |
| output-high; | |
| pinmux = <0x9800>; | |
| }; | |
| }; | |
| reset1_active { | |
| phandle = <0x1e3>; | |
| pins_cmd_dat { | |
| output-high; | |
| pinmux = <0x9800>; | |
| }; | |
| }; | |
| lcm_dsi_te { | |
| phandle = <0x1d1>; | |
| pins_cmd_dat { | |
| pinmux = <0x5301>; | |
| }; | |
| }; | |
| camera_pins_cam1_mclk_4ma { | |
| phandle = <0x1c2>; | |
| pins_cmd_dat { | |
| drive-strength = <0x01>; | |
| pinmux = <0x7e01>; | |
| }; | |
| }; | |
| eintdefault { | |
| phandle = <0x1db>; | |
| }; | |
| int_active { | |
| phandle = <0x1dc>; | |
| pins_cmd_dat { | |
| pinmux = <0x900>; | |
| input-enable; | |
| }; | |
| }; | |
| cam0@1 { | |
| phandle = <0x1b6>; | |
| pins_cmd_dat { | |
| slew-rate = <0x01>; | |
| output-high; | |
| pinmux = <0x1400>; | |
| }; | |
| }; | |
| aud_dat_miso1_off { | |
| phandle = <0x72>; | |
| pins_cmd1_dat { | |
| bias-disable; | |
| pinmux = <0xb000>; | |
| input-enable; | |
| }; | |
| }; | |
| camera_pins_cam1_mclk_8ma { | |
| phandle = <0x1c4>; | |
| pins_cmd_dat { | |
| drive-strength = <0x03>; | |
| pinmux = <0x7e01>; | |
| }; | |
| }; | |
| gps_l1_lna@2 { | |
| phandle = <0x1d7>; | |
| pins_cmd_dat { | |
| output-high; | |
| pinmux = <0x1900>; | |
| }; | |
| }; | |
| gps_l1_lna@0 { | |
| phandle = <0x1d5>; | |
| pins_cmd_dat { | |
| output-low; | |
| pinmux = <0x1900>; | |
| }; | |
| }; | |
| mmc1@1 { | |
| phandle = <0x87>; | |
| pins_clk { | |
| drive-strength = <0x03>; | |
| bias-pull-down = <0x66>; | |
| pinmux = <0x4701>; | |
| }; | |
| pins_cmd_dat { | |
| drive-strength = <0x03>; | |
| bias-pull-down = <0x66>; | |
| pinmux = <0x4901 0x4a01 0x4b01 0x4c01 0x4801>; | |
| input-enable; | |
| }; | |
| }; | |
| aud_gpio_i2s3_on { | |
| phandle = <0x77>; | |
| pins_cmd3_dat { | |
| input-schmitt-enable; | |
| bias-disable; | |
| pinmux = <0x3402>; | |
| }; | |
| pins_cmd1_dat { | |
| input-schmitt-enable; | |
| bias-disable; | |
| pinmux = <0x3202>; | |
| }; | |
| pins_cmd2_dat { | |
| input-schmitt-enable; | |
| bias-disable; | |
| pinmux = <0x3302>; | |
| }; | |
| }; | |
| aud_clk_mosi_on { | |
| phandle = <0x6b>; | |
| pins_cmd0_dat { | |
| input-schmitt-enable; | |
| bias-disable; | |
| pinmux = <0xa901>; | |
| }; | |
| }; | |
| i2cmode_default { | |
| phandle = <0x1e0>; | |
| pins_cmd_dat { | |
| pinmux = <0x8201 0x8301>; | |
| }; | |
| }; | |
| int1_active { | |
| phandle = <0x1e2>; | |
| pins_cmd_dat { | |
| pinmux = <0x900>; | |
| input-enable; | |
| }; | |
| }; | |
| aud_dat_mosi_on { | |
| phandle = <0x6f>; | |
| pins_cmd0_dat { | |
| input-schmitt-enable; | |
| bias-disable; | |
| pinmux = <0xab01>; | |
| }; | |
| pins_cmd1_dat { | |
| input-schmitt-enable; | |
| bias-disable; | |
| pinmux = <0xac01>; | |
| }; | |
| }; | |
| aud_gpio_i2s0_on { | |
| phandle = <0x75>; | |
| pins_cmd1_dat { | |
| input-schmitt-enable; | |
| bias-disable; | |
| pinmux = <0x3502>; | |
| }; | |
| }; | |
| reset1_suspend { | |
| phandle = <0x1e5>; | |
| pins_cmd_dat { | |
| output-low; | |
| pinmux = <0x9800>; | |
| }; | |
| }; | |
| vow_dat_miso_on { | |
| phandle = <0x79>; | |
| pins_cmd1_dat { | |
| input-schmitt-enable; | |
| bias-disable; | |
| pinmux = <0xaf04>; | |
| }; | |
| }; | |
| camera_pins_cam0_mclk_2ma { | |
| phandle = <0x1bc>; | |
| pins_cmd_dat { | |
| drive-strength = <0x00>; | |
| pinmux = <0x8001>; | |
| }; | |
| }; | |
| aud_clk_miso_on { | |
| phandle = <0x6d>; | |
| pins_cmd0_dat { | |
| input-schmitt-enable; | |
| bias-disable; | |
| pinmux = <0xad01>; | |
| }; | |
| }; | |
| aud_dat_miso0_off { | |
| phandle = <0x70>; | |
| pins_cmd1_dat { | |
| bias-pull-down; | |
| pinmux = <0xaf00>; | |
| input-enable; | |
| }; | |
| }; | |
| camera_pins_cam2_mclk_6ma { | |
| phandle = <0x1c8>; | |
| pins_cmd_dat { | |
| drive-strength = <0x02>; | |
| pinmux = <0x8101>; | |
| }; | |
| }; | |
| camera_pins_cam2_mclk_off { | |
| phandle = <0x1c5>; | |
| pins_cmd_dat { | |
| drive-strength = <0x01>; | |
| pinmux = <0x8100>; | |
| }; | |
| }; | |
| mmc0default { | |
| phandle = <0x82>; | |
| pins_rst { | |
| drive-strength = <0x04>; | |
| pinmux = <0x3901>; | |
| bias-pull-up = <0x64>; | |
| }; | |
| pins_clk { | |
| drive-strength = <0x04>; | |
| bias-pull-down = <0x66>; | |
| pinmux = <0x3701>; | |
| }; | |
| pins_cmd_dat { | |
| drive-strength = <0x04>; | |
| pinmux = <0x3a01 0x3b01 0x3c01 0x3d01 0x3e01 0x3f01 0x4001 0x4101 0x3801>; | |
| bias-pull-up = <0x65>; | |
| input-enable; | |
| }; | |
| }; | |
| camera_pins_cam2_mclk_2ma { | |
| phandle = <0x1c6>; | |
| pins_cmd_dat { | |
| drive-strength = <0x00>; | |
| pinmux = <0x8101>; | |
| }; | |
| }; | |
| vow_clk_miso_off { | |
| phandle = <0x7a>; | |
| pins_cmd1_dat { | |
| bias-pull-down; | |
| pinmux = <0xb000>; | |
| input-enable; | |
| }; | |
| }; | |
| aud_dat_mosi_off { | |
| phandle = <0x6e>; | |
| pins_cmd0_dat { | |
| bias-pull-down; | |
| pinmux = <0xab00>; | |
| input-enable; | |
| }; | |
| pins_cmd1_dat { | |
| bias-pull-down; | |
| pinmux = <0xac00>; | |
| input-enable; | |
| }; | |
| }; | |
| lcm_rst_out0_gpio { | |
| phandle = <0x1d0>; | |
| pins_cmd_dat { | |
| output-low; | |
| slew-rate = <0x01>; | |
| pinmux = <0x5500>; | |
| }; | |
| }; | |
| cam2@0 { | |
| phandle = <0x1b9>; | |
| pins_cmd_dat { | |
| output-low; | |
| slew-rate = <0x01>; | |
| pinmux = <0x1600>; | |
| }; | |
| }; | |
| gps_l5_lna@0 { | |
| phandle = <0x1d8>; | |
| pins_cmd_dat { | |
| output-low; | |
| pinmux = <0x1a00>; | |
| }; | |
| }; | |
| mmc0@1 { | |
| phandle = <0x84>; | |
| pins_rst { | |
| drive-strength = <0x04>; | |
| pinmux = <0x3901>; | |
| bias-pull-up = <0x64>; | |
| }; | |
| pins_clk { | |
| drive-strength = <0x04>; | |
| bias-pull-down = <0x66>; | |
| pinmux = <0x3701>; | |
| }; | |
| pins_cmd_dat { | |
| drive-strength = <0x04>; | |
| bias-pull-down = <0x66>; | |
| pinmux = <0x3a01 0x3b01 0x3c01 0x3d01 0x3e01 0x3f01 0x4001 0x4101 0x3801>; | |
| input-enable; | |
| }; | |
| }; | |
| aud_dat_miso1_on { | |
| phandle = <0x73>; | |
| pins_cmd1_dat { | |
| input-schmitt-enable; | |
| bias-disable; | |
| pinmux = <0xb001>; | |
| }; | |
| }; | |
| gps_l5_lna@1 { | |
| phandle = <0x1d9>; | |
| pins_cmd_dat { | |
| pinmux = <0x1a02>; | |
| }; | |
| }; | |
| gps_l5_lna@2 { | |
| phandle = <0x1da>; | |
| pins_cmd_dat { | |
| output-high; | |
| pinmux = <0x1a00>; | |
| }; | |
| }; | |
| lcm_led_en0_gpio { | |
| phandle = <0x1ce>; | |
| pins_cmd_dat { | |
| output-low; | |
| slew-rate = <0x01>; | |
| pinmux = <0x9a00>; | |
| }; | |
| }; | |
| aud_clk_mosi_off { | |
| phandle = <0x6a>; | |
| pins_cmd0_dat { | |
| bias-pull-down; | |
| pinmux = <0xa900>; | |
| input-enable; | |
| }; | |
| }; | |
| vow_dat_miso_off { | |
| phandle = <0x78>; | |
| pins_cmd1_dat { | |
| bias-pull-down; | |
| pinmux = <0xaf00>; | |
| input-enable; | |
| }; | |
| }; | |
| camera_pins_cam1_mclk_6ma { | |
| phandle = <0x1c3>; | |
| pins_cmd_dat { | |
| drive-strength = <0x02>; | |
| pinmux = <0x7e01>; | |
| }; | |
| }; | |
| camera_pins_cam0_mclk_off { | |
| phandle = <0x1bb>; | |
| pins_cmd_dat { | |
| drive-strength = <0x01>; | |
| pinmux = <0x8000>; | |
| }; | |
| }; | |
| gps_default { | |
| phandle = <0x1d4>; | |
| }; | |
| camera_pins_cam1_mclk_2ma { | |
| phandle = <0x1c1>; | |
| pins_cmd_dat { | |
| drive-strength = <0x00>; | |
| pinmux = <0x7e01>; | |
| }; | |
| }; | |
| camera_pins_cam0_mclk_6ma { | |
| phandle = <0x1be>; | |
| pins_cmd_dat { | |
| drive-strength = <0x02>; | |
| pinmux = <0x8001>; | |
| }; | |
| }; | |
| camera_pins_cam2_mclk_4ma { | |
| phandle = <0x1c7>; | |
| pins_cmd_dat { | |
| drive-strength = <0x01>; | |
| pinmux = <0x8101>; | |
| }; | |
| }; | |
| mmc0@0 { | |
| phandle = <0x83>; | |
| pins_rst { | |
| drive-strength = <0x04>; | |
| pinmux = <0x3901>; | |
| bias-pull-up = <0x64>; | |
| }; | |
| pins_ds { | |
| drive-strength = <0x04>; | |
| bias-pull-down = <0x66>; | |
| pinmux = <0x3601>; | |
| }; | |
| pins_clk { | |
| drive-strength = <0x04>; | |
| bias-pull-down = <0x66>; | |
| pinmux = <0x3701>; | |
| }; | |
| pins_cmd_dat { | |
| drive-strength = <0x04>; | |
| pinmux = <0x3a01 0x3b01 0x3c01 0x3d01 0x3e01 0x3f01 0x4001 0x4101 0x3801>; | |
| bias-pull-up = <0x65>; | |
| input-enable; | |
| }; | |
| }; | |
| aud_gpio_i2s0_off { | |
| phandle = <0x74>; | |
| pins_cmd1_dat { | |
| bias-pull-down; | |
| pinmux = <0x3500>; | |
| input-enable; | |
| }; | |
| }; | |
| camera_pins_cam2_mclk_8ma { | |
| phandle = <0x1c9>; | |
| pins_cmd_dat { | |
| drive-strength = <0x03>; | |
| pinmux = <0x8101>; | |
| }; | |
| }; | |
| mmc1default { | |
| phandle = <0x85>; | |
| pins_clk { | |
| drive-strength = <0x03>; | |
| bias-pull-down = <0x66>; | |
| pinmux = <0x4701>; | |
| }; | |
| pins_cmd_dat { | |
| drive-strength = <0x03>; | |
| pinmux = <0x4901 0x4a01 0x4b01 0x4c01 0x4801>; | |
| bias-pull-up = <0x65>; | |
| input-enable; | |
| }; | |
| }; | |
| camdefault { | |
| phandle = <0x1b4>; | |
| }; | |
| hwen_low { | |
| phandle = <0x1e9>; | |
| pins_cmd_dat { | |
| output-low; | |
| slew-rate = <0x01>; | |
| pinmux = <0x9d00>; | |
| }; | |
| }; | |
| cam1@1 { | |
| phandle = <0x1b8>; | |
| pins_cmd_dat { | |
| slew-rate = <0x01>; | |
| output-high; | |
| pinmux = <0x1000>; | |
| }; | |
| }; | |
| aud_gpio_i2s3_off { | |
| phandle = <0x76>; | |
| pins_cmd3_dat { | |
| bias-pull-down; | |
| pinmux = <0x3400>; | |
| input-enable; | |
| }; | |
| pins_cmd1_dat { | |
| bias-pull-down; | |
| pinmux = <0x3200>; | |
| input-enable; | |
| }; | |
| pins_cmd2_dat { | |
| bias-pull-down; | |
| pinmux = <0x3300>; | |
| input-enable; | |
| }; | |
| }; | |
| vow_clk_miso_on { | |
| phandle = <0x7b>; | |
| pins_cmd1_dat { | |
| input-schmitt-enable; | |
| bias-disable; | |
| pinmux = <0xb004>; | |
| }; | |
| }; | |
| spimode_default { | |
| phandle = <0x1e6>; | |
| pins_cmd_dat { | |
| drive-strength = <0x02>; | |
| pinmux = <0x1e01 0x1f01 0x2001 0x2101>; | |
| }; | |
| }; | |
| camera_pins_cam1_mclk_off { | |
| phandle = <0x1c0>; | |
| pins_cmd_dat { | |
| drive-strength = <0x01>; | |
| pinmux = <0x7e00>; | |
| }; | |
| }; | |
| lcm_rst_out1_gpio { | |
| phandle = <0x1cf>; | |
| pins_cmd_dat { | |
| slew-rate = <0x01>; | |
| output-high; | |
| pinmux = <0x5500>; | |
| }; | |
| }; | |
| aud_dat_miso0_on { | |
| phandle = <0x71>; | |
| pins_cmd1_dat { | |
| input-schmitt-enable; | |
| bias-disable; | |
| pinmux = <0xaf01>; | |
| }; | |
| }; | |
| camera_pins_cam0_mclk_8ma { | |
| phandle = <0x1bf>; | |
| pins_cmd_dat { | |
| drive-strength = <0x03>; | |
| pinmux = <0x8001>; | |
| }; | |
| }; | |
| gps_l1_lna@1 { | |
| phandle = <0x1d6>; | |
| pins_cmd_dat { | |
| pinmux = <0x1902>; | |
| }; | |
| }; | |
| fan_control_set_off { | |
| phandle = <0x1ee>; | |
| pins_cmd0_dat { | |
| output-low; | |
| input-schmitt-enable = <0x00>; | |
| slew-rate = <0x01>; | |
| bias-pull-down = <0x0b>; | |
| pinmux = <0x2100>; | |
| }; | |
| pins_cmd1_dat { | |
| output-low; | |
| input-schmitt-enable = <0x00>; | |
| slew-rate = <0x01>; | |
| bias-pull-down = <0x0b>; | |
| pinmux = <0x9700>; | |
| }; | |
| }; | |
| default { | |
| phandle = <0x1e7>; | |
| }; | |
| int1_suspend { | |
| phandle = <0x1e4>; | |
| pins_cmd_dat { | |
| output-low; | |
| pinmux = <0x900>; | |
| }; | |
| }; | |
| pins_default { | |
| phandle = <0x1e1>; | |
| }; | |
| }; | |
| devapc_ao_infra_peri@10022000 { | |
| compatible = "mediatek,devapc_ao_infra_peri"; | |
| reg = <0x00 0x10022000 0x00 0x1000>; | |
| }; | |
| dip_a3@15024000 { | |
| compatible = "mediatek,dip_a3"; | |
| reg = <0x00 0x15024000 0x00 0x1000>; | |
| }; | |
| iommu@14017000 { | |
| compatible = "mediatek,common-disp-iommu-bank1"; | |
| reg = <0x00 0x14017000 0x00 0x1000>; | |
| phandle = <0xa5>; | |
| interrupts = <0x00 0x130 0x04 0x00>; | |
| mediatek,bank-id = <0x01>; | |
| }; | |
| gpufreq { | |
| clock-names = "clk_mux\0clk_ref_mux\0clk_main_parent\0clk_sub_parent\0subsys_bg3d"; | |
| _vsram_gpu-supply = <0x8e>; | |
| _vgpu-supply = <0x8d>; | |
| compatible = "mediatek,gpufreq"; | |
| nvmem-cell-names = "efuse_segment_cell"; | |
| nvmem-cells = <0x8f>; | |
| reg = <0x00 0x13fbf000 0x00 0x1000 0x00 0x10006000 0x00 0x1000 0x00 0x1021c000 0x00 0x1000 0x00 0x1020e000 0x00 0x1000 0x00 0x10042000 0x00 0x1000 0x00 0x10001000 0x00 0x1000 0x00 0x10023000 0x00 0x1000 0x00 0x1002b000 0x00 0x1000 0x00 0x10000000 0x00 0x1000 0x00 0x11c10000 0x00 0x1000 0x00 0x10215000 0x00 0x1000>; | |
| clocks = <0x2a 0x0a 0x2a 0x09 0x2a 0x4a 0x2a 0x91 0x8c 0x00>; | |
| phandle = <0x92>; | |
| fhctl-supply = <0x90>; | |
| gpufreq_wrapper-supply = <0x91>; | |
| reg-names = "mfg_top_config\0sleep\0nth_emicfg_reg\0infracfg\0fmem_ao_debug_ctrl\0infracfg_ao\0infra_ao_debug_ctrl\0infra_ao1_debug_ctrl\0topckgen\0efuse\0infra_bcrm"; | |
| }; | |
| mobicore { | |
| compatible = "trustonic,mobicore"; | |
| phandle = <0x150>; | |
| interrupts = <0x00 0x73 0x01 0x00>; | |
| }; | |
| smi_larb2@1f002000 { | |
| clock-names = "apb\0smi"; | |
| compatible = "mediatek,smi_larb2\0mediatek,mt6789-smi-larb\0mediatek,smi-larb"; | |
| mediatek,smi = <0x9b>; | |
| mediatek,larb-id = <0x02>; | |
| reg = <0x00 0x1f002000 0x00 0x1000>; | |
| clocks = <0x2c 0x04 0x2c 0x04>; | |
| phandle = <0x95>; | |
| power-domains = <0x2d 0x0a>; | |
| }; | |
| mtk_leds { | |
| compatible = "mediatek,pwm-leds"; | |
| phandle = <0x114>; | |
| backlight { | |
| max-brightness = <0xff>; | |
| pwm_config = <0x00 0x01 0x00 0x00 0x00>; | |
| pwms = <0x17d 0x00 0x99d9>; | |
| led_mode = <0x05>; | |
| label = "lcd-backlight"; | |
| pwm-names = "lcd-backlight"; | |
| max-hw-brightness = <0x7ff>; | |
| }; | |
| }; | |
| mdp@1f000000 { | |
| mdp_hdr0_sof = <0x104>; | |
| dip_cq_thread9_frame_done = <0xea>; | |
| mdp_rsz0_frame_done = <0x12b>; | |
| g3d_config_base = <0x13000000 0x00 0xffff0000>; | |
| mdp_rdma0 = <0xaf>; | |
| mdp_wrot0_sof = <0x107>; | |
| dip_cq_thread17_frame_done = <0xf2>; | |
| mdp-dvfsrc-vcore-supply = <0x42>; | |
| img_dl_relay1_sof = <0x10c>; | |
| gce_base = <0x18020000 0x18 0xffff0000>; | |
| dip_cq_thread10_frame_done = <0xeb>; | |
| mdp_aal_sof = <0x102>; | |
| mdp_rsz1_frame_done = <0x12a>; | |
| operating-points-v2 = <0xb7 0xb8>; | |
| scp_sram_base = <0x10000000 0x0a 0xffff0000>; | |
| mdp_wrot0 = <0xb2>; | |
| mdp_wrot1_write_frame_done = <0x122>; | |
| kp_base = <0x18840000 0x09 0xffff0000>; | |
| mediatek,larb = <0x95>; | |
| mdp_tdshp_sof = <0x109>; | |
| dip_cq_thread6_frame_done = <0xe7>; | |
| dre30_hist_sram_start = [06 00]; | |
| camsys_base = <0x18080000 0x1b 0xffff0000>; | |
| usb_sif_base = <0x10280000 0x11 0xffff0000>; | |
| vdec3_base = <0x18050000 0x1a 0xffff0000>; | |
| mdp_rsz0 = <0xb0>; | |
| venc_gcon_base = <0x18810000 0x06 0xffff0000>; | |
| compatible = "mediatek,mdp"; | |
| vdec2_base = <0x18040000 0x19 0xffff0000>; | |
| dip_cq_thread0_frame_done = <0xe1>; | |
| mboxes = <0x68 0x0a 0x00 0x01 0x66 0x10 0x00 0x01 0x66 0x11 0x00 0x01 0x66 0x12 0x00 0x01 0x66 0x13 0x00 0x01>; | |
| dip_cq_thread4_frame_done = <0xe5>; | |
| mmsys_config_base = <0x14000000 0x01 0xffff0000>; | |
| dip_cq_thread5_frame_done = <0xe6>; | |
| mm_mutex = <0xae>; | |
| mdp_rsz1_sof = <0x106>; | |
| dip_cq_thread2_frame_done = <0xe3>; | |
| mcucfg_base = <0x10040000 0x0e 0xffff0000>; | |
| dip_cq_thread15_frame_done = <0xf0>; | |
| infra_na3_base = <0x10010000 0x0b 0xffff0000>; | |
| isp-dvfsrc-vcore-supply = <0x42>; | |
| mdp_hdr0_frame_done = <0x131>; | |
| interconnect-names = "mdp_rdma0\0mdp_wrot0\0mdp_wrot1\0l9_img_imgi_d1\0l9_img_imgbi_d1\0l9_img_dmgi_d1\0l9_img_depi_d1\0l9_img_ice_d1\0l9_img_smti_d1\0l9_img_smto_d2\0l9_img_smto_d1\0l9_img_crzo_d1\0l9_img_img3o_d1\0l9_img_vipi_d1\0l9_img_smti_d5\0l9_img_timgo_d1\0l9_img_ufbc_w0\0l9_img_ufbc_r0"; | |
| mdp_tdshp0 = <0xb4>; | |
| img_dl_relay_sof = <0x10b>; | |
| dip_cq_thread13_frame_done = <0xee>; | |
| msdc2_base = <0x17020000 0x14 0xffff0000>; | |
| mmsys_config = <0xad>; | |
| vdec1_base = <0x17030000 0x15 0xffff0000>; | |
| pq_rb_event_lock = [02 b6]; | |
| vdec_gcon_base = <0x18800000 0x05 0xffff0000>; | |
| reg = <0x00 0x1f000000 0x00 0x1000>; | |
| dip_cq_thread7_frame_done = <0xe8>; | |
| dip_cq_thread14_frame_done = <0xef>; | |
| gcpu_base = <0x10050000 0x0f 0xffff0000>; | |
| ap_dma_base = <0x18010000 0x17 0xffff0000>; | |
| phandle = <0x191>; | |
| disp_dither_base = <0x14010000 0x02 0xffff0000>; | |
| mdp_wrot0_write_frame_done = <0x123>; | |
| mdp_hdr0 = <0xb6>; | |
| msdc3_base = <0x18000000 0x16 0xffff0000>; | |
| interconnects = <0xa3 0x40040 0xa3 0x10000 0xa3 0x40042 0xa3 0x10000 0xa3 0x40043 0xa3 0x10000 0xa3 0x40120 0xa3 0x10000 0xa3 0x40121 0xa3 0x10000 0xa3 0x40122 0xa3 0x10000 0xa3 0x40123 0xa3 0x10000 0xa3 0x40124 0xa3 0x10000 0xa3 0x40125 0xa3 0x10000 0xa3 0x40126 0xa3 0x10000 0xa3 0x40127 0xa3 0x10000 0xa3 0x40128 0xa3 0x10000 0xa3 0x40129 0xa3 0x10000 0xa3 0x4012a 0xa3 0x10000 0xa3 0x4012b 0xa3 0x10000 0xa3 0x4012c 0xa3 0x10000 0xa3 0x4012d 0xa3 0x10000 0xa3 0x4012e 0xa3 0x10000>; | |
| audio_base = <0x17000000 0x12 0xffff0000>; | |
| infra_na4_base = <0x10020000 0x0c 0xffff0000>; | |
| mdp-opp = <0xb7>; | |
| mdp_rdma0_sof = <0x100>; | |
| mdp_aal_frame_done = <0x136>; | |
| dip_cq_thread12_frame_done = <0xed>; | |
| scp_base = <0x10030000 0x0d 0xffff0000>; | |
| mdp_rsz0_sof = <0x105>; | |
| usb0_base = <0x10200000 0x10 0xffff0000>; | |
| isp-opp = <0xb8>; | |
| mdp_rdma0_frame_done = <0x12f>; | |
| mdp_rsz1 = <0xb1>; | |
| mdp_aal0 = <0xb5>; | |
| camsys1_base = <0x180a0000 0x1c 0xffff0000>; | |
| dip_cq_thread18_frame_done = <0xf3>; | |
| topckgen_base = <0x18830000 0x08 0xffff0000>; | |
| dip_cq_thread3_frame_done = <0xe4>; | |
| mdp_tdshp_frame_done = <0x127>; | |
| conn_peri_base = <0x18820000 0x07 0xffff0000>; | |
| vdec_base = <0x17010000 0x13 0xffff0000>; | |
| dip_cq_thread11_frame_done = <0xec>; | |
| mdp_wrot1 = <0xb3>; | |
| pq_rb_event_unlock = [02 b7]; | |
| dip_cq_thread1_frame_done = <0xe2>; | |
| pq_rb_thread_id = [00 13]; | |
| mdp_wrot1_sof = <0x108>; | |
| mm_na_base = <0x14020000 0x03 0xffff0000>; | |
| dip_cq_thread16_frame_done = <0xf1>; | |
| thread_count = <0x18>; | |
| dip_cq_thread8_frame_done = <0xe9>; | |
| imgsys_base = <0x15020000 0x04 0xffff0000>; | |
| }; | |
| fe@1b002000 { | |
| compatible = "mediatek,fe"; | |
| reg = <0x00 0x1b002000 0x00 0x1000>; | |
| interrupts = <0x00 0x189 0x04 0x00>; | |
| }; | |
| reserved@14011000 { | |
| compatible = "mediatek,reserved"; | |
| reg = <0x00 0x14011000 0x00 0x1000>; | |
| }; | |
| dip_a2@15023000 { | |
| compatible = "mediatek,dip_a2"; | |
| reg = <0x00 0x15023000 0x00 0x1000>; | |
| }; | |
| usb_boost_manager { | |
| compatible = "mediatek,usb_boost\0mediatek,mt6789-usb_boost"; | |
| required-opps = <0x23>; | |
| small-core = <0x13d620>; | |
| interconnect-names = "icc-bw"; | |
| phandle = <0x19b>; | |
| interconnects = <0x22 0x17 0x22 0x00>; | |
| }; | |
| dsi@14013000 { | |
| phys = <0xa4>; | |
| clock-names = "engine\0digital\0hs"; | |
| #size-cells = <0x00>; | |
| compatible = "mediatek,dsi0\0mediatek,mt6789-dsi"; | |
| status = "okay"; | |
| #address-cells = <0x01>; | |
| reg = <0x00 0x14013000 0x00 0x1000>; | |
| phy-names = "dphy"; | |
| clocks = <0x35 0x10 0x35 0x15 0xa4>; | |
| phandle = <0x18b>; | |
| interrupts = <0x00 0x12d 0x04 0x00>; | |
| ports { | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x1d3>; | |
| phandle = <0x1d2>; | |
| }; | |
| }; | |
| }; | |
| panel1@0 { | |
| compatible = "jty,ft8707,fhd,boe"; | |
| pm-enable-gpios = <0x49 0x9a 0x00>; | |
| pinctrl-names = "default"; | |
| reset-gpios = <0x49 0x55 0x00>; | |
| reg = <0x00>; | |
| bias-gpios = <0x49 0x9b 0x00 0x49 0x9e 0x00>; | |
| port { | |
| endpoint { | |
| remote-endpoint = <0x1d2>; | |
| phandle = <0x1d3>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| infracfg_mem@1021c000 { | |
| compatible = "mediatek,infracfg_mem"; | |
| reg = <0x00 0x1021c000 0x00 0x1000>; | |
| }; | |
| pwm@10048000 { | |
| clock-names = "PWM1-main\0PWM2-main\0PWM3-main\0PWM-HCLK-main\0PWM-main"; | |
| mediatek,pwm2-bclk-sw-ctrl-offset = <0x02>; | |
| mediatek,pwm3-bclk-sw-ctrl-offset = <0x04>; | |
| pwmsrcclk = <0x2b>; | |
| mediatek,pwm1-bclk-sw-ctrl-offset = <0x00>; | |
| mediatek,pwm-version = <0x02>; | |
| mediatek,pwm-bclk-sw-ctrl-offset = <0x0c>; | |
| compatible = "mediatek,pwm"; | |
| reg = <0x00 0x10048000 0x00 0x1000>; | |
| clocks = <0x2b 0x08 0x2b 0x09 0x2b 0x0a 0x2b 0x07 0x2b 0x0c>; | |
| mediatek,pwm-topclk-ctl-reg = <0x410>; | |
| interrupts = <0x00 0xf2 0x04 0x00>; | |
| }; | |
| mtk_iommu_fake_aie@0 { | |
| iommus = <0x43 0x24>; | |
| compatible = "mediatek,mtk_iommu_fake_aie"; | |
| }; | |
| ap_ccif2@1023c000 { | |
| compatible = "mediatek,ap_ccif2"; | |
| reg = <0x00 0x1023c000 0x00 0x1000>; | |
| }; | |
| vdec@16000000 { | |
| svp-mtee = <0x01>; | |
| mediatek,clock-parents = <0x04 0x03>; | |
| clock-names = "CORE_MT_CG_VDEC0"; | |
| iommus = <0x43 0x10080 0x43 0x10081 0x43 0x10082 0x43 0x10083 0x43 0x10084 0x43 0x10085 0x43 0x10086 0x43 0x10087 0x43 0x10088 0x43 0x10089 0x43 0x1008b 0x43 0x1008a>; | |
| operating-points-v2 = <0xa9>; | |
| throughput-normal-max = <0x1298be00>; | |
| m4u-ports = <0x10080 0x10081 0x10082 0x10083 0x10084 0x10085 0x10086 0x10087 0x10088 0x10089 0x1008b 0x1008a>; | |
| interconnect-num = <0x0d>; | |
| throughput-op-rate-thresh = <0x78>; | |
| compatible = "mediatek,mt6789-vcodec-dec"; | |
| mediatek,platform = "platform:mt6789"; | |
| dma-ranges = <0x01 0x00 0x01 0x00 0x01 0x00>; | |
| mediatek,vcu = <0xac>; | |
| bandwidth-table = <0x03 0x44c 0x03 0x00 0x02 0x226 0x05 0x0a 0x05 0x0a 0x05 0x00 0x05 0x00 0x00 0x1a 0x00 0x1a 0x05 0x1a 0x05 0x00 0x06 0x04>; | |
| profile-target = <0x0f 0x19 0x1e 0x32 0x3c 0x5a 0x78 0x96 0xb4 0xf0 0x1e0>; | |
| interconnect-names = "path_vdec_mc\0path_vdec_ufo\0path_vdec_pp\0path_vdec_pred_rd\0path_vdec_pred_wr\0path_vdec_ppwrap\0path_vdec_tile\0path_vdec_vld\0path_vdec_vld2\0path_vdec_avc_mv\0path_vdec_ufo_c\0path_vdec_rg_ctrl_dma\0path_larb4"; | |
| throughput-table = <0x3447504d 0x00 0x282 0x282 0x3147504d 0x00 0x255 0x255 0x3247504d 0x00 0x255 0x255 0x33363248 0x00 0x255 0x255 0x34363248 0x00 0x27d 0x27d 0x31435641 0x00 0x27d 0x27d 0x43564548 0x00 0x27d 0x27d 0x35363248 0x00 0x27d 0x27d 0x46494548 0x00 0x27d 0x27d 0x30385056 0x00 0x255 0x255 0x30395056 0x00 0x27d 0x27d 0x30315641 0x00 0x27d 0x27d>; | |
| max-op-rate-table = <0x3447504d 0xe1000 0x28 0x384000 0x1e 0x870000 0x1e 0x3147504d 0xe1000 0x28 0x384000 0x1e 0x870000 0x1e 0x3247504d 0xe1000 0x28 0x384000 0x1e 0x870000 0x1e 0x33363248 0xe1000 0x28 0x384000 0x11 0x870000 0x05 0x34363248 0xe1000 0x28 0x384000 0x1e 0x870000 0x1e 0x31435641 0xe1000 0x28 0x384000 0x1e 0x870000 0x1e 0x43564548 0xe1000 0x28 0x384000 0x1e 0x870000 0x1e 0x35363248 0xe1000 0x28 0x384000 0x1e 0x870000 0x1e 0x46494548 0x40000 0x226 0x200000 0x226 0x870000 0x3c 0x30385056 0xe1000 0x28 0x384000 0x1e 0x870000 0x1e 0x30395056 0xe1000 0x28 0x384000 0x1e 0x870000 0x1e 0x30315641 0xe1000 0x28 0x384000 0x1e 0x870000 0x1e>; | |
| m4u-port-names = "M4U_PORT_VDEC_MC\0M4U_PORT_VDEC_UFO\0M4U_PORT_VDEC_PP\0M4U_PORT_VDEC_PRED_RD\0M4U_PORT_VDEC_PRED_WR\0M4U_PORT_VDEC_PPWRAP\0M4U_PORT_VDEC_TILE\0M4U_PORT_VDEC_VLD\0M4U_PORT_VDEC_VLD2\0M4U_PORT_VDEC_AVC_MV\0M4U_PORT_VDEC_RG_CTRL_DMA\0M4U_PORT_VDEC_UFO_ENC"; | |
| throughput-min = <0xcfe6a80>; | |
| mediatek,ipm = <0x01>; | |
| reg = <0x00 0x16000000 0x00 0x1000 0x00 0x1602f000 0x00 0x1000 0x00 0x16020000 0x00 0x1000 0x00 0x16021000 0x00 0x1000 0x00 0x16023000 0x00 0x1000 0x00 0x16025000 0x00 0x4000>; | |
| dvfsrc-vcore-supply = <0x42>; | |
| clocks = <0x33 0x05>; | |
| interconnects = <0xa3 0x40080 0xa3 0x10000 0xa3 0x40081 0xa3 0x10000 0xa3 0x40082 0xa3 0x10000 0xa3 0x40083 0xa3 0x10000 0xa3 0x40084 0xa3 0x10000 0xa3 0x40085 0xa3 0x10000 0xa3 0x40086 0xa3 0x10000 0xa3 0x40087 0xa3 0x10000 0xa3 0x40088 0xa3 0x10000 0xa3 0x40089 0xa3 0x10000 0xa3 0x4008a 0xa3 0x10000 0xa3 0x4008b 0xa3 0x10000 0xa3 0x30004 0xa3 0x10000>; | |
| profile-duration = <0x3c 0x7d0>; | |
| reg-names = "VDEC_BASE\0VDEC_SYS\0VDEC_VLD\0VDEC_MC\0VDEC_MV\0VDEC_MISC"; | |
| mediatek,larbs = <0x96>; | |
| interrupts = <0x00 0x1ca 0x04 0x00>; | |
| }; | |
| topckgen_ao@1001b000 { | |
| compatible = "mediatek,topckgen_ao"; | |
| reg = <0x00 0x1001b000 0x00 0x1000>; | |
| }; | |
| apirq@1000b000 { | |
| mediatek,total-pin-number = <0xa0>; | |
| reg-name = "eint"; | |
| compatible = "mediatek,mt6983-eint"; | |
| reg = <0x00 0x1000b000 0x00 0x1000>; | |
| phandle = <0x4a>; | |
| mediatek,instance-num = <0x01>; | |
| interrupts = <0x00 0xf4 0x04 0x00>; | |
| }; | |
| infracfg_ao@10001000 { | |
| compatible = "mediatek,infracfg_ao\0syscon"; | |
| reg = <0x00 0x10001000 0x00 0x1000>; | |
| phandle = <0xbd>; | |
| }; | |
| infra_dpmaif@1022d000 { | |
| compatible = "mediatek,infra_dpmaif"; | |
| reg = <0x00 0x1022d000 0x00 0x1000>; | |
| }; | |
| i2c@11eb1000 { | |
| clock-names = "main\0dma"; | |
| clock-div = <0x01>; | |
| #size-cells = <0x00>; | |
| compatible = "mediatek,mt6983-i2c"; | |
| status = "okay"; | |
| #address-cells = <0x01>; | |
| reg = <0x00 0x11eb1000 0x00 0x1000 0x00 0x10217300 0x00 0x80>; | |
| clocks = <0x37 0x01 0x2b 0x3d>; | |
| phandle = <0x15f>; | |
| clock-frequency = <0x61a80>; | |
| interrupts = <0x00 0x94 0x04 0x00>; | |
| camera_eeprom1@51 { | |
| compatible = "mediatek,camera_eeprom"; | |
| status = "okay"; | |
| reg = <0x51>; | |
| phandle = <0x1f1>; | |
| }; | |
| camera_sub@1a { | |
| compatible = "mediatek,camera_sub"; | |
| #thermal-sensor-cells = <0x00>; | |
| status = "okay"; | |
| reg = <0x1a>; | |
| phandle = <0x1cb>; | |
| }; | |
| }; | |
| seninf_top@1a004000 { | |
| clock-names = "CAMSYS_SENINF_CGPDN\0TOP_MUX_SENINF\0TOP_MUX_SENINF1\0TOP_MUX_SENINF2\0TOP_MUX_SENINF3\0TOP_MUX_CAMTG\0TOP_MUX_CAMTG2\0TOP_MUX_CAMTG3\0TOP_MUX_CAMTG4\0TOP_CLK26M\0TOP_UNIVP_192M_D8\0TOP_UNIVPLL_D6_D8\0TOP_UNIVP_192M_D4\0TOP_F26M_CK_D2\0TOP_UNIVP_192M_D16\0TOP_UNIVP_192M_D32"; | |
| operating-points-v2 = <0x41>; | |
| compatible = "mediatek,seninf_top"; | |
| mediatek,platform = "mt6789"; | |
| reg = <0x00 0x1a004000 0x00 0x1000>; | |
| dvfsrc-vcore-supply = <0x42>; | |
| clocks = <0x31 0x04 0x2a 0x1f 0x2a 0x20 0x2a 0x21 0x2a 0x22 0x2a 0x0b 0x2a 0x0c 0x2a 0x0d 0x2a 0x0e 0x2a 0x82 0x2a 0x6b 0x2a 0x66 0x2a 0x6a 0x2a 0x83 0x2a 0x6c 0x2a 0x6d>; | |
| phandle = <0x119>; | |
| mediatek,seninf_max_num = "6"; | |
| power-domains = <0x2d 0x0c>; | |
| }; | |
| iommu@14018000 { | |
| compatible = "mediatek,common-disp-iommu-bank2"; | |
| reg = <0x00 0x14018000 0x00 0x1000>; | |
| phandle = <0xa6>; | |
| interrupts = <0x00 0x131 0x04 0x00>; | |
| mediatek,bank-id = <0x02>; | |
| }; | |
| dip_b9@1582a000 { | |
| compatible = "mediatek,dip_b9"; | |
| reg = <0x00 0x1582a000 0x00 0x1000>; | |
| }; | |
| ufshci@11270000 { | |
| clock-names = "ufs\0ufs_mp\0unipro_tick\0unipro_sys\0ufs_aes\0ufsfde_ck\0ufs_ck"; | |
| freq-table-hz = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; | |
| compatible = "mediatek,mt8183-ufshci"; | |
| resets = <0x7e 0x01 0x7e 0x02 0x7e 0x03>; | |
| reset-names = "hci_rst\0unipro_rst\0crypto_rst"; | |
| vcc-supply = <0x81>; | |
| reg = <0x00 0x11270000 0x00 0x2300>; | |
| clocks = <0x2b 0x2f 0x2b 0x2b 0x2b 0x2a 0x2b 0x29 0x2b 0x30 0x2a 0x26 0x2a 0x27>; | |
| phandle = <0x176>; | |
| bootmode = <0x50>; | |
| interrupts = <0x00 0x89 0x04 0x00>; | |
| mediatek,ufs-qos; | |
| }; | |
| mtk_iommu_pseudo { | |
| compatible = "mediatek,mt6789-iommu-pseudo"; | |
| mediatek,larbs = <0x93 0x94 0x95 0x96 0x97 0x98 0x44 0x99 0x45 0x46 0x9a>; | |
| }; | |
| kd_camera_hw1@1a004000 { | |
| pinctrl-6 = <0x1ba>; | |
| cam2_vcamd-supply = <0x168>; | |
| cam1_vcama-supply = <0x167>; | |
| pinctrl-15 = <0x1c3>; | |
| cam1_pin_mclk = "mclk"; | |
| pinctrl-11 = <0x1bf>; | |
| pinctrl-14 = <0x1c2>; | |
| cam1_pin_vcamaf = "regulator"; | |
| cam1_vcama1-supply = <0x166>; | |
| cam1_pin_vcamd = "regulator"; | |
| cam1_pin_vcamio = "regulator"; | |
| pinctrl-5 = <0x1b9>; | |
| pinctrl-12 = <0x1c0>; | |
| cam2_vcamio-supply = <0x65>; | |
| cam0_pin_vcamd = "regulator"; | |
| cam0_vcamio-supply = <0x65>; | |
| cam1_pin_vcama1 = "regulator"; | |
| compatible = "mediatek,imgsensor"; | |
| pinctrl-8 = <0x1bc>; | |
| cam2_pin_vcama1 = "regulator"; | |
| pinctrl-20 = <0x1c8>; | |
| pinctrl-19 = <0x1c7>; | |
| cam0_vcama1-supply = <0x166>; | |
| cam2_pin_mclk = "mclk"; | |
| cam1_vcamd-supply = <0x168>; | |
| cam1_vcamio-supply = <0x65>; | |
| pinctrl-1 = <0x1b5>; | |
| pinctrl-names = "default\0cam0_rst0\0cam0_rst1\0cam1_rst0\0cam1_rst1\0cam2_rst0\0cam2_rst1\0cam0_mclk_off\0cam0_mclk_2mA\0cam0_mclk_4mA\0cam0_mclk_6mA\0cam0_mclk_8mA\0cam1_mclk_off\0cam1_mclk_2mA\0cam1_mclk_4mA\0cam1_mclk_6mA\0cam1_mclk_8mA\0cam2_mclk_off\0cam2_mclk_2mA\0cam2_mclk_4mA\0cam2_mclk_6mA\0cam2_mclk_8mA"; | |
| cam1_pin_rst = "gpio"; | |
| cam2_pin_rst = "gpio"; | |
| status = "okay"; | |
| cam0_pin_rst = "gpio"; | |
| pinctrl-2 = <0x1b6>; | |
| cam2_pin_vcamd = "regulator"; | |
| cam0_vcama-supply = <0x165>; | |
| pinctrl-16 = <0x1c4>; | |
| pinctrl-13 = <0x1c1>; | |
| cam0_pin_vcamaf = "regulator"; | |
| pinctrl-7 = <0x1bb>; | |
| cam0_pin_vcama = "regulator"; | |
| cam0_pin_vcama1 = "regulator"; | |
| phandle = <0x11a>; | |
| pinctrl-17 = <0x1c5>; | |
| cam0_vcamd-supply = <0x169>; | |
| cam2_pin_vcamio = "regulator"; | |
| cam1_pin_vcama = "regulator"; | |
| cam2_pin_vcamaf = "gpio"; | |
| cam0_vcamaf-supply = <0x164>; | |
| pinctrl-10 = <0x1be>; | |
| cam2_vcama-supply = <0x195>; | |
| cam0_pin_mclk = "mclk"; | |
| pinctrl-18 = <0x1c6>; | |
| cam2_pin_vcama = "regulator"; | |
| pinctrl-4 = <0x1b8>; | |
| pinctrl-0 = <0x1b4>; | |
| pinctrl-21 = <0x1c9>; | |
| cam1_vcamaf-supply = <0x163>; | |
| pinctrl-9 = <0x1bd>; | |
| cam0_pin_vcamio = "regulator"; | |
| cam2_vcamaf-supply = <0x194>; | |
| cam2_vcama1-supply = <0x166>; | |
| pinctrl-3 = <0x1b7>; | |
| }; | |
| sramrom@10214000 { | |
| compatible = "mediatek,sramrom"; | |
| reg = <0x00 0x10214000 0x00 0x1000>; | |
| }; | |
| smi_pd_cam_rawa { | |
| mediatek,comm-port-range = <0x04>; | |
| compatible = "mediatek,smi-pd"; | |
| mediatek,smi = <0x9f>; | |
| power-reset = <0x1a04f00c 0x00>; | |
| phandle = <0x17a>; | |
| power-domains = <0x2d 0x0d>; | |
| }; | |
| reserved@14015000 { | |
| compatible = "mediatek,reserved"; | |
| reg = <0x00 0x14015000 0x00 0x1000>; | |
| }; | |
| i2c@11eb0000 { | |
| clock-names = "main\0dma"; | |
| clock-div = <0x01>; | |
| #size-cells = <0x00>; | |
| compatible = "mediatek,mt6983-i2c"; | |
| status = "okay"; | |
| #address-cells = <0x01>; | |
| reg = <0x00 0x11eb0000 0x00 0x1000 0x00 0x10217180 0x00 0x80>; | |
| clocks = <0x37 0x00 0x2b 0x3d>; | |
| phandle = <0x15d>; | |
| clock-frequency = <0x61a80>; | |
| interrupts = <0x00 0x92 0x04 0x00>; | |
| camera_main_three_af@0c { | |
| compatible = "mediatek,camera_main_three_af"; | |
| status = "okay"; | |
| reg = <0x0c>; | |
| phandle = <0x1f9>; | |
| }; | |
| camera_main_two_af@0d { | |
| compatible = "mediatek,camera_main_two_af"; | |
| status = "okay"; | |
| reg = <0x0d>; | |
| phandle = <0x1f8>; | |
| }; | |
| camera_eeprom2@51 { | |
| compatible = "mediatek,camera_eeprom"; | |
| status = "okay"; | |
| reg = <0x51>; | |
| phandle = <0x1f0>; | |
| }; | |
| camera_main_two@10 { | |
| compatible = "mediatek,camera_main_two"; | |
| #thermal-sensor-cells = <0x00>; | |
| status = "okay"; | |
| reg = <0x10>; | |
| phandle = <0x1cc>; | |
| }; | |
| }; | |
| g3d_config@13fbf000 { | |
| compatible = "mediatek,g3d_config"; | |
| reg = <0x00 0x13fbf000 0x00 0x1000>; | |
| }; | |
| md_ccif4@1024d000 { | |
| compatible = "mediatek,md_ccif4"; | |
| reg = <0x00 0x1024d000 0x00 0x1000>; | |
| }; | |
| mtk_iommu_test1 { | |
| iommus = <0x43 0x10080>; | |
| compatible = "mediatek,iommu-test-dom1"; | |
| dma-ranges = <0x00 0x00 0x00 0x00 0x04 0x00>; | |
| }; | |
| consys@18002000 { | |
| clock-names = "ccif"; | |
| emi-alignment = <0x1000000>; | |
| #size-cells = <0x02>; | |
| compatible = "mediatek,mt6789-consys"; | |
| #thermal-sensor-cells = <0x00>; | |
| #address-cells = <0x02>; | |
| reg = <0x00 0x18002000 0x00 0x1000 0x00 0x10007000 0x00 0x100 0x00 0x10001000 0x00 0x1000 0x00 0x10006000 0x00 0x1000 0x00 0x18007000 0x00 0x1000 0x00 0x180b1000 0x00 0x1000 0x00 0x180a3000 0x00 0x1000 0x00 0x180a5000 0x00 0x800 0x00 0x180c1000 0x00 0x1000 0x00 0x18004000 0x00 0x1000 0x00 0x1024c000 0x00 0x40 0x00 0x10003000 0x00 0x1000>; | |
| clocks = <0x2b 0x38>; | |
| phandle = <0x21>; | |
| emi-addr = <0x7e000000>; | |
| emi-size = <0x500000>; | |
| pmic = <0xab>; | |
| emi-max-addr = <0x80000000>; | |
| power-domains = <0x2d 0x01>; | |
| interrupts = <0x00 0x19a 0x04 0x00 0x00 0x6f 0x04 0x00 0x00 0x19b 0x04 0x00>; | |
| }; | |
| cam_smi_3x1_sub_comm1@1a00c000 { | |
| clock-names = "apb\0smi\0gals0\0gals1"; | |
| mediatek,common-id = <0x06>; | |
| compatible = "mediatek,mt6789-smi-common\0syscon\0mediatek,smi-common\0mediatek,smi-sub-common"; | |
| mediatek,smi = <0x9b>; | |
| reg = <0x00 0x1a00c000 0x00 0x1000>; | |
| clocks = <0x31 0x01 0x31 0x02 0x31 0x01 0x31 0x02>; | |
| phandle = <0x9f>; | |
| power-domains = <0x2d 0x0c>; | |
| }; | |
| seninf4@1a007000 { | |
| compatible = "mediatek,seninf4"; | |
| reg = <0x00 0x1a007000 0x00 0x1000>; | |
| }; | |
| dip_a1@15022000 { | |
| compatible = "mediatek,dip_a1"; | |
| reg = <0x00 0x15022000 0x00 0x1000>; | |
| }; | |
| snd_scp_audio { | |
| scp_spk_process_enable = <0x00 0x04 0x0f 0x13>; | |
| compatible = "mediatek,snd_scp_audio"; | |
| status = "disabled"; | |
| phandle = <0x7d>; | |
| }; | |
| spi0@1100a000 { | |
| clock-names = "parent-clk\0sel-clk\0spi-clk"; | |
| pinctrl-5 = <0x1e6>; | |
| #size-cells = <0x00>; | |
| compatible = "mediatek,mt6789-spi"; | |
| pinctrl-1 = <0x1e2>; | |
| pinctrl-names = "default\0gt9896s_int_active\0gt9896s_reset_active\0gt9896s_int_suspend\0gt9896s_reset_suspend\0gt9896s_spi_mode"; | |
| mediatek,pad-select = <0x00>; | |
| status = "okay"; | |
| pinctrl-2 = <0x1e3>; | |
| #address-cells = <0x01>; | |
| reg = <0x00 0x1100a000 0x00 0x100>; | |
| clocks = <0x2a 0x7f 0x2a 0x12 0x2b 0x13>; | |
| phandle = <0x152>; | |
| pinctrl-4 = <0x1e5>; | |
| pinctrl-0 = <0x1e1>; | |
| interrupts = <0x00 0xbf 0x04 0x00>; | |
| pinctrl-3 = <0x1e4>; | |
| gt9896s@0 { | |
| goodix,input-max-x = <0x438>; | |
| goodix,panel-key-map = <0x9e 0xac 0xd9>; | |
| goodix,x2x; | |
| goodix,firmware-version = "6789v01"; | |
| goodix,reset-gpio = <0x49 0x98 0x00>; | |
| goodix,irq-gpio = <0x49 0x09 0x00>; | |
| spi-max-frequency = <0xf4240>; | |
| goodix,pen-enable; | |
| tpd-filter-enable = <0x00>; | |
| goodix,panel-max-id = <0x0a>; | |
| compatible = "goodix,gt9896s"; | |
| goodix,panel-max-y = <0x960>; | |
| goodix,panel-max-w = <0x100>; | |
| goodix,config-version = "6789v01"; | |
| goodix,power-off-delay-us = <0x1388>; | |
| tpd-filter-custom-speed = <0x00 0x00 0x00>; | |
| goodix,irq-flags = <0x02>; | |
| goodix,input-max-y = <0x960>; | |
| goodix,avdd-name = "vtouch"; | |
| reg = <0x00>; | |
| goodix,y2y; | |
| goodix,panel-max-p = <0x100>; | |
| tpd-filter-custom-prameters = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; | |
| goodix,power-on-delay-us = <0x2710>; | |
| goodix,panel-max-x = <0x438>; | |
| vtouch-supply = <0x135>; | |
| tpd-filter-pixel-density = <0xa1>; | |
| }; | |
| }; | |
| scp_clk_ctrl@10721000 { | |
| compatible = "mediatek,scp_clk_ctrl\0syscon"; | |
| reg = <0x00 0x10721000 0x00 0x1000>; | |
| phandle = <0x5b>; | |
| }; | |
| ccci_scp { | |
| clock-names = "infra-ccif2-ap\0infra-ccif2-md"; | |
| compatible = "mediatek,ccci_md_scp"; | |
| reg = <0x00 0x1023c000 0x00 0x1000 0x00 0x1023d000 0x00 0x1000>; | |
| clocks = <0x2b 0x34 0x2b 0x35>; | |
| phandle = <0x149>; | |
| }; | |
| mddriver { | |
| mediatek,ap_plat_info = <0x1a85>; | |
| mediatek,offset_epon_md1 = <0x24 0x06>; | |
| md1_ccb_cap_gear = <0x01>; | |
| md_vmodem = <0xc96a8 0xc96a8>; | |
| md_vmodem-supply = <0x5d>; | |
| ccci_spmsleep = <0x5c>; | |
| ccci-infracfg = <0x2b>; | |
| md1_ccb_gear_list = "1(2,20);2(2,10);3(0,0);4(2,30);6(2,50);11(2,2);12(2,62)"; | |
| md_vsram = <0xc96a8 0xc96a8>; | |
| compatible = "mediatek,mddriver"; | |
| mediatek,md_generation = <0x1897>; | |
| mediatek,mdhif_type = <0x06>; | |
| ccci-topckgen = <0x2a>; | |
| mediatek,cldma_capability = <0x06>; | |
| mediatek,power_flow_config = <0x12>; | |
| reg = <0x00 0xd0cf000 0x00 0x1000>; | |
| mediatek,srclken_o1 = <0x200000>; | |
| phandle = <0xd1>; | |
| mediatek,md_id = <0x00>; | |
| ccci,modem_info_v2 = <0xf0febf 0x00 0x10180000 0x00 0x3000000 0x1b000000 0x1000000 0x00 0x00 0x00 0x00 0x00>; | |
| power-domains = <0x2d 0x00>; | |
| interrupts = <0x00 0x6e 0x01 0x00 0x00 0xe2 0x04 0x00 0x00 0xe3 0x04 0x00>; | |
| md_vsram-supply = <0x5e>; | |
| }; | |
| disp_postmask0@1400e000 { | |
| iommus = <0x43 0x00>; | |
| mediatek,larb = <0x93>; | |
| compatible = "mediatek,disp_postmask0\0mediatek,mt6789-disp-postmask"; | |
| mediatek,smi-id = <0x00>; | |
| reg = <0x00 0x1400e000 0x00 0x1000>; | |
| clocks = <0x35 0x0d>; | |
| phandle = <0x188>; | |
| interrupts = <0x00 0x128 0x04 0x00>; | |
| }; | |
| sleep@10006000 { | |
| compatible = "mediatek,sleep"; | |
| spmfw_version = "suspend_moet_V14 "; | |
| reg = <0x00 0x10006000 0x00 0xa00>; | |
| interrupts = <0x00 0xff 0x04 0x00>; | |
| }; | |
| g3d_dvfs@13fbb000 { | |
| compatible = "mediatek,g3d_dvfs"; | |
| reg = <0x00 0x13fbb000 0x00 0x1000>; | |
| }; | |
| scp_audio_mbox@107ff000 { | |
| compatible = "mediatek,scp_audio_mbox"; | |
| status = "disabled"; | |
| reg = <0x00 0x107ff000 0x00 0x100 0x00 0x107ff100 0x00 0x04 0x00 0x107ff10c 0x00 0x04>; | |
| phandle = <0x174>; | |
| interrupt-names = "mbox0"; | |
| reg-names = "mbox0_base\0mbox0_set\0mbox0_clr"; | |
| interrupts = <0x00 0x1d8 0x04 0x00>; | |
| }; | |
| disp_mtee_sec { | |
| compatible = "mediatek,disp_mtee"; | |
| mboxes = <0x68 0x08 0x00 0x03 0x68 0x09 0x00 0x03 0x68 0x09 0x00 0x03>; | |
| phandle = <0x17e>; | |
| mediatek,mailbox-gce = <0x66>; | |
| gce-client-names = "CLIENT_SEC_CFG0\0CLIENT_SEC_CFG1\0CLIENT_SEC_CFG2"; | |
| }; | |
| dip_a8@15029000 { | |
| compatible = "mediatek,dip_a8"; | |
| reg = <0x00 0x15029000 0x00 0x1000>; | |
| }; | |
| seninf2@1a005000 { | |
| compatible = "mediatek,seninf2"; | |
| reg = <0x00 0x1a005000 0x00 0x1000>; | |
| }; | |
| disp_pwm0@1100e000 { | |
| clock-names = "main\0mm\0pwm_src"; | |
| compatible = "mediatek,disp_pwm0\0mediatek,mt6789-disp-pwm"; | |
| reg = <0x00 0x1100e000 0x00 0x1000>; | |
| clocks = <0x2b 0x23 0x2a 0x1c 0x2a 0x85>; | |
| phandle = <0x17d>; | |
| #pwm-cells = <0x02>; | |
| interrupts = <0x00 0xcb 0x04 0x00>; | |
| }; | |
| pmu { | |
| compatible = "arm,armv8-pmuv3"; | |
| interrupt-parent = <0x01>; | |
| interrupts = <0x01 0x07 0x04 0x00>; | |
| }; | |
| disp_gamma0@1400d000 { | |
| color_protect_red = <0x00>; | |
| color_protect_black = <0x00>; | |
| color_protect_blue = <0x00>; | |
| compatible = "mediatek,disp_gamma0\0mediatek,mt6789-disp-gamma"; | |
| color_protect_green = <0x00>; | |
| gamma_data_mode = <0x02>; | |
| color_protect_white = <0x00>; | |
| reg = <0x00 0x1400d000 0x00 0x1000>; | |
| clocks = <0x35 0x0c>; | |
| phandle = <0x187>; | |
| interrupts = <0x00 0x127 0x04 0x00>; | |
| color_protect_lsb = <0x00>; | |
| }; | |
| reserved@1f00d000 { | |
| compatible = "mediatek,reserved"; | |
| reg = <0x00 0x1f00d000 0x00 0x1000>; | |
| }; | |
| spi3@11013000 { | |
| clock-names = "parent-clk\0sel-clk\0spi-clk"; | |
| compatible = "mediatek,mt6789-spi"; | |
| mediatek,pad-select = <0x00>; | |
| reg = <0x00 0x11013000 0x00 0x100>; | |
| clocks = <0x2a 0x7f 0x2a 0x12 0x2b 0x28>; | |
| phandle = <0x155>; | |
| interrupts = <0x00 0xc2 0x04 0x00>; | |
| }; | |
| dip_b2@15823000 { | |
| compatible = "mediatek,dip_b2"; | |
| reg = <0x00 0x15823000 0x00 0x1000>; | |
| }; | |
| infra_bcrm@10215000 { | |
| compatible = "mediatek,infra_bcrm"; | |
| reg = <0x00 0x10215000 0x00 0x1000>; | |
| }; | |
| reserved@1f006000 { | |
| compatible = "mediatek,reserved"; | |
| reg = <0x00 0x1f006000 0x00 0x1000>; | |
| }; | |
| efuse@11c10000 { | |
| #size-cells = <0x01>; | |
| compatible = "mediatek,devinfo"; | |
| #address-cells = <0x01>; | |
| reg = <0x00 0x11c10000 0x00 0x10000>; | |
| phandle = <0x69>; | |
| data1 { | |
| reg = <0x1b4 0x2c>; | |
| phandle = <0x7f>; | |
| }; | |
| data2 { | |
| reg = <0x2f8 0x08>; | |
| phandle = <0x80>; | |
| }; | |
| segment@78 { | |
| reg = <0x78 0x04>; | |
| phandle = <0x8f>; | |
| }; | |
| u2_phy_data { | |
| reg = <0x1b0 0x04>; | |
| phandle = <0xbf>; | |
| }; | |
| lkg { | |
| reg = <0x218 0x18>; | |
| phandle = <0x40>; | |
| }; | |
| }; | |
| mtk_sec_dmaheap { | |
| iommus = <0x43 0x00>; | |
| compatible = "mediatek,dmaheap-region-base"; | |
| }; | |
| aie@1b001000 { | |
| clock-names = "aie\0FDVT_CLK_IPE_LARB20"; | |
| iommus = <0x43 0x20280 0x43 0x20281 0x43 0x20282 0x43 0x20283>; | |
| fdvt_frame_done = <0xb1>; | |
| mediatek,larb = <0x9a>; | |
| compatible = "mediatek,mt6789-aie\0mediatek,aie-hw2.0"; | |
| mboxes = <0x66 0x14 0x00 0x01 0x68 0x0b 0x00 0x01>; | |
| dma-ranges = <0x02 0x00 0x02 0x00 0x01 0x00>; | |
| reg = <0x00 0x1b001000 0x00 0x1000>; | |
| clocks = <0x2e 0x03 0x2e 0x01>; | |
| power-domains = <0x2d 0x07>; | |
| interrupts = <0x00 0x187 0x04 0x00>; | |
| }; | |
| mipi_tx_config@11f60000 { | |
| #phy-cells = <0x00>; | |
| compatible = "mediatek,mipi_tx_config0\0mediatek,mt6789-mipi-tx"; | |
| clock-output-names = "mipi_tx0_pll"; | |
| reg = <0x00 0x11f60000 0x00 0x1000>; | |
| clocks = <0x55>; | |
| phandle = <0xa4>; | |
| #clock-cells = <0x00>; | |
| }; | |
| smi_larb16@1a00f000 { | |
| clock-names = "apb\0smi"; | |
| compatible = "mediatek,smi_larb16\0mediatek,mt6789-smi-larb\0mediatek,smi-larb"; | |
| mediatek,smi = <0x9f>; | |
| mediatek,larb-id = <0x10>; | |
| reg = <0x00 0x1a00f000 0x00 0x1000>; | |
| clocks = <0x30 0x00 0x30 0x01>; | |
| phandle = <0x45>; | |
| power-domains = <0x2d 0x0d>; | |
| }; | |
| mtk_iommu_test_dmaheap_normal { | |
| iommus = <0x43 0x00>; | |
| compatible = "mediatek,dmaheap-normal"; | |
| }; | |
| mmqos_wrapper { | |
| compatible = "mediatek,mt6789-mmqos-wrapper"; | |
| }; | |
| usb_meta { | |
| compatible = "mediatek,usb_meta"; | |
| phandle = <0x19c>; | |
| udc = <0x64>; | |
| }; | |
| cmdq-test { | |
| token_gpr_set4 = [02 c0]; | |
| compatible = "mediatek,cmdq-test"; | |
| token_user0 = [02 89]; | |
| mboxes = <0x66 0x0a 0x00 0x01 0x66 0x0b 0xffffffff 0x01 0x68 0x0c 0x00 0x01>; | |
| mediatek,gce = <0x66>; | |
| mmsys_config = <0x67>; | |
| mediatek,gce-subsys = <0x63 0x01>; | |
| }; | |
| seninf_n3d_top@1a004000 { | |
| clock-names = "CAMSYS_SENINF_CGPDN\0CAMSYS_CAM_CGPDN\0CAMSYS_CAMTG_CGPDN\0CAMSYS_CAMTM_SEL"; | |
| compatible = "mediatek,seninf_n3d_top"; | |
| reg = <0x00 0x1a004000 0x00 0x100 0x00 0x1a004100 0x00 0x100 0x00 0x1a004200 0x00 0x100>; | |
| clocks = <0x31 0x04 0x31 0x02 0x31 0x03 0x2a 0x2d>; | |
| phandle = <0x11b>; | |
| reg-names = "seninf_top\0seninf_n3d_a\0seninf_n3d_b"; | |
| power-domains = <0x2d 0x0c>; | |
| interrupts = <0x00 0x15f 0x04 0x00>; | |
| }; | |
| i2c@1101a000 { | |
| clock-names = "main\0dma"; | |
| clock-div = <0x01>; | |
| compatible = "mediatek,mt6983-i2c"; | |
| reg = <0x00 0x1101a000 0x00 0x1000 0x00 0x10217480 0x00 0x80>; | |
| clocks = <0x3a 0x02 0x2b 0x3d>; | |
| phandle = <0x16a>; | |
| interrupts = <0x00 0x96 0x04 0x00>; | |
| aw87xxx_pa_58@58 { | |
| compatible = "awinic,aw87xxx_pa"; | |
| reset-gpio = <0x49 0x99 0x00>; | |
| status = "okay"; | |
| reg = <0x58>; | |
| pa-channel = <0x01>; | |
| }; | |
| aw87xxx_pa_59@59 { | |
| compatible = "awinic,aw87xxx_pa"; | |
| reset-gpio = <0x49 0x9c 0x00>; | |
| status = "okay"; | |
| reg = <0x59>; | |
| pa-channel = <0x00>; | |
| }; | |
| lm3643@63 { | |
| compatible = "mediatek,lm3643"; | |
| pinctrl-1 = <0x1e8>; | |
| pinctrl-names = "default\0hwen_high\0hwen_low"; | |
| status = "okay"; | |
| #cooling-cells = <0x02>; | |
| pinctrl-2 = <0x1e9>; | |
| reg = <0x63>; | |
| phandle = <0x1f6>; | |
| pinctrl-0 = <0x1e7>; | |
| flash@1 { | |
| part = <0x00>; | |
| ct = <0x01>; | |
| reg = <0x01>; | |
| type = <0x00>; | |
| port@1 { | |
| endpoint { | |
| remote-endpoint = <0x1eb>; | |
| phandle = <0x1ed>; | |
| }; | |
| }; | |
| }; | |
| flash@0 { | |
| part = <0x00>; | |
| ct = <0x00>; | |
| reg = <0x00>; | |
| type = <0x00>; | |
| port@0 { | |
| endpoint { | |
| remote-endpoint = <0x1ea>; | |
| phandle = <0x1ec>; | |
| }; | |
| }; | |
| }; | |
| }; | |
| gate_ic@11 { | |
| gate-power-gpios = <0x49 0x0c 0x00>; | |
| id = <0x06>; | |
| compatible = "mediatek,gate-ic-i2c"; | |
| status = "okay"; | |
| reg = <0x11>; | |
| phandle = <0x16b>; | |
| }; | |
| }; | |
| dramc_ch1_rsv@10940000 { | |
| compatible = "mediatek,dramc_ch1_rsv"; | |
| reg = <0x00 0x10940000 0x00 0xc0000>; | |
| }; | |
| seninf5@1a008000 { | |
| compatible = "mediatek,seninf5"; | |
| reg = <0x00 0x1a008000 0x00 0x1000>; | |
| }; | |
| ipesys_config@1b000000 { | |
| compatible = "mediatek,ipesys_config"; | |
| reg = <0x00 0x1b000000 0x00 0x1000>; | |
| }; | |
| md_ccif0@1020a000 { | |
| compatible = "mediatek,md_ccif0"; | |
| reg = <0x00 0x1020a000 0x00 0x1000>; | |
| }; | |
| mfb@15010000 { | |
| compatible = "mediatek,mfb"; | |
| reg = <0x00 0x15010000 0x00 0x1000>; | |
| interrupts = <0x00 0x17c 0x04 0x00>; | |
| }; | |
| bus_dbg@10208000 { | |
| compatible = "mediatek,bus_dbg"; | |
| reg = <0x00 0x10208000 0x00 0x1000>; | |
| }; | |
| disp_ccorr0@1400b000 { | |
| ccorr_bit = <0x0d>; | |
| ccorr_linear_per_pipe = <0x01>; | |
| compatible = "mediatek,disp_ccorr0\0mediatek,mt6789-disp-ccorr"; | |
| ccorr_num_per_pipe = <0x01>; | |
| reg = <0x00 0x1400b000 0x00 0x1000>; | |
| clocks = <0x35 0x08>; | |
| phandle = <0x185>; | |
| interrupts = <0x00 0x124 0x04 0x00>; | |
| }; | |
| img1_smi_2x1_sub_comm@1401e000 { | |
| clock-names = "apb\0smi\0gals0\0gals1"; | |
| mediatek,common-id = <0x03>; | |
| compatible = "mediatek,mt6789-smi-common\0syscon\0mediatek,smi-common\0mediatek,smi-sub-common"; | |
| mediatek,smi = <0x9b>; | |
| reg = <0x00 0x1401e000 0x00 0x1000>; | |
| clocks = <0x35 0x0a 0x35 0x0f 0x35 0x13 0x35 0x14>; | |
| phandle = <0x9e>; | |
| power-domains = <0x2d 0x0a>; | |
| }; | |
| dip_a10@1502b000 { | |
| compatible = "mediatek,dip_a10"; | |
| reg = <0x00 0x1502b000 0x00 0x1000>; | |
| }; | |
| reserved@1400a000 { | |
| compatible = "mediatek,reserved"; | |
| reg = <0x00 0x1400a000 0x00 0x1000>; | |
| }; | |
| iommu@14016000 { | |
| clock-names = "bclk"; | |
| mediatek,iommu_banks = <0xa5 0xa6 0xa7 0xa8>; | |
| compatible = "mediatek,mt6789-disp-iommu"; | |
| #iommu-cells = <0x01>; | |
| reg = <0x00 0x14016000 0x00 0x1000>; | |
| clocks = <0x35 0x14>; | |
| phandle = <0x43>; | |
| power-domains = <0x2d 0x0a>; | |
| mediatek,larbs = <0x93 0x94 0x95 0x96 0x97 0x98 0x44 0x99 0x45 0x46 0x9a>; | |
| interrupts = <0x00 0x12f 0x04 0x00>; | |
| }; | |
| performance-controller@0011bc00 { | |
| compatible = "mediatek,cpufreq-hw"; | |
| #performance-domain-cells = <0x01>; | |
| reg = <0x00 0x11bc10 0x00 0x120 0x00 0x11bd30 0x00 0x120>; | |
| phandle = <0x02>; | |
| reg-names = "performance-domain0\0performance-domain1"; | |
| }; | |
| mbist_ao@10013000 { | |
| compatible = "mediatek,mbist_ao"; | |
| reg = <0x00 0x10013000 0x00 0x1000>; | |
| }; | |
| emimpu@10226000 { | |
| dram_start = <0x00 0x40000000>; | |
| compatible = "mediatek,common-emimpu"; | |
| ctrl_intf = <0x01>; | |
| clear = <0x160 0xffffffff 0x10 0x200 0x03 0x10 0x1f0 0x80000000 0x01>; | |
| dram_end = <0x01 0xbfffffff>; | |
| clear_md = <0x1fc 0x80000000 0x01>; | |
| addr_align = <0x10>; | |
| reg = <0x00 0x10226000 0x00 0x1000>; | |
| phandle = <0x118>; | |
| interrupts = <0x00 0xdd 0x04 0x00>; | |
| region_cnt = <0x20>; | |
| slverr = <0x00>; | |
| mediatek,emi-reg = <0x4c>; | |
| dump = <0x1f0 0x1f8 0x1fc>; | |
| domain_cnt = <0x10>; | |
| }; | |
| spi5@11019000 { | |
| clock-names = "parent-clk\0sel-clk\0spi-clk"; | |
| compatible = "mediatek,mt6789-spi"; | |
| mediatek,pad-select = <0x00>; | |
| reg = <0x00 0x11019000 0x00 0x100>; | |
| clocks = <0x2a 0x7f 0x2a 0x12 0x2b 0x2d>; | |
| phandle = <0x157>; | |
| interrupts = <0x00 0xc4 0x04 0x00>; | |
| }; | |
| wpe_a@15011000 { | |
| compatible = "mediatek,wpe_a"; | |
| reg = <0x00 0x15011000 0x00 0x1000>; | |
| interrupts = <0x00 0x17d 0x04 0x00>; | |
| }; | |
| dip_a11@1502c000 { | |
| compatible = "mediatek,dip_a11"; | |
| reg = <0x00 0x1502c000 0x00 0x1000>; | |
| }; | |
| smi_larb0@14003000 { | |
| clock-names = "apb\0smi\0gals0\0gals1"; | |
| compatible = "mediatek,smi_larb0\0mediatek,mt6789-smi-larb\0mediatek,smi-larb"; | |
| mediatek,smi = <0x9b>; | |
| mediatek,larb-id = <0x00>; | |
| reg = <0x00 0x14003000 0x00 0x1000>; | |
| clocks = <0x35 0x0a 0x35 0x0f 0x35 0x13 0x35 0x14>; | |
| phandle = <0x93>; | |
| power-domains = <0x2d 0x0a>; | |
| }; | |
| gce_mbox_sec@10228000 { | |
| clock-names = "gce"; | |
| #mbox-cells = <0x03>; | |
| compatible = "mediatek,mailbox-gce-sec"; | |
| mboxes = <0x66 0x0f 0xffffffff 0x01>; | |
| reg = <0x00 0x10228000 0x00 0x4000>; | |
| clocks = <0x2b 0x02>; | |
| phandle = <0x68>; | |
| }; | |
| mdp_wrot1@1f00b000 { | |
| clock-names = "MDP_WROT1"; | |
| compatible = "mediatek,mdp_wrot1"; | |
| reg = <0x00 0x1f00b000 0x00 0x1000>; | |
| clocks = <0x2c 0x0a>; | |
| phandle = <0xb3>; | |
| }; | |
| security_ao@1001a000 { | |
| compatible = "mediatek,security_ao"; | |
| reg = <0x00 0x1001a000 0x00 0x1000>; | |
| }; | |
| infracfg@1020e000 { | |
| compatible = "mediatek,infracfg"; | |
| reg = <0x00 0x1020e000 0x00 0x1000>; | |
| }; | |
| interconnect { | |
| mediatek,commons = <0x9b>; | |
| clock-names = "mm"; | |
| compatible = "mediatek,mt6789-mmqos"; | |
| interconnect-names = "icc-bw\0icc-hrt-bw"; | |
| #mtk-interconnect-cells = <0x01>; | |
| clocks = <0x2a 0x04>; | |
| phandle = <0xa3>; | |
| interconnects = <0x22 0x08 0x22 0x00 0x22 0x1a 0x22 0x19>; | |
| mediatek,larbs = <0x93 0x94 0x95 0x96 0x97 0x98 0x44 0x99 0x45 0x46 0x9a>; | |
| }; | |
| emi@10219000 { | |
| compatible = "mediatek,emi"; | |
| reg = <0x00 0x10219000 0x00 0x1000>; | |
| interrupts = <0x00 0xdd 0x04 0x00>; | |
| }; | |
| teeperf { | |
| compatible = "mediatek,teeperf"; | |
| cpu-map = <0x02>; | |
| cpu-type = <0x02>; | |
| }; | |
| smi_test { | |
| compatible = "mediatek,smi-testcase"; | |
| mediatek,larbs = <0x95>; | |
| }; | |
| cam_smi_4x1_sub_comm0@1a00d000 { | |
| clock-names = "apb\0smi\0gals0\0gals1"; | |
| mediatek,common-id = <0x07>; | |
| compatible = "mediatek,mt6789-smi-common\0syscon\0mediatek,smi-common\0mediatek,smi-sub-common"; | |
| mediatek,smi = <0x9b>; | |
| reg = <0x00 0x1a00d000 0x00 0x1000>; | |
| clocks = <0x31 0x00 0x31 0x02 0x31 0x00 0x31 0x02>; | |
| phandle = <0xa0>; | |
| power-domains = <0x2d 0x0c>; | |
| }; | |
| scp_dvfs { | |
| secure_access = "enable"; | |
| clock-names = "clk_mux\0clk_pll_0\0clk_pll_1\0clk_pll_2\0clk_pll_3\0clk_pll_4\0clk_pll_5\0clk_pll_6\0clk_pll_7"; | |
| clk-dbg-ver = "v1"; | |
| scp_dvfs_flag = "enable"; | |
| gpio-vreq-mode = <0x01>; | |
| scp-clk-hw-ver = "v1"; | |
| sshub-vcore-supply = <0x59>; | |
| no-pmic-rg-access; | |
| compatible = "mediatek,scp_dvfs"; | |
| ulposc-cali-ver = "v1"; | |
| do-ulposc-cali; | |
| scp-cores = <0x01>; | |
| dvfsrc-vscp-supply = <0x57>; | |
| fmeter_clksys = <0x2a>; | |
| ulposc_clksys = <0x3b>; | |
| scp_clk_ctrl = <0x5b>; | |
| clocks = <0x2a 0x02 0x2a 0x82 0x2a 0x5c 0x2a 0x7c 0x2a 0x54 0x2a 0x63 0x2a 0x4c 0x2a 0x4b 0x2a 0x57>; | |
| sshub-vsram-supply = <0x5a>; | |
| ccf-fmeter-support; | |
| gpio-base = <0x58>; | |
| dvfs-opp = <0x86470 0xb71b0 0x00 0x10 0xfa 0x00 0x00 0x927c0 0xb71b0 0x01 0x108 0x14a 0x07 0x00 0x9eb10 0xb71b0 0x02 0x204 0x190 0x03 0x00 0xb1008 0xb71b0 0x03 0x302 0x270 0x01 0x03>; | |
| ulposc-cali-num = <0x03>; | |
| ulposc-cali-config = <0x38a940 0x2900 0x41 0x52a940 0x2900 0x41 0x5ea940 0x2900 0x41>; | |
| ulposc-cali-target = <0xfa 0x14a 0x190>; | |
| pmic-sshub-support; | |
| gpio-vreq = <0x440 0x07 0x18>; | |
| }; | |
| wpe_b@15811000 { | |
| compatible = "mediatek,wpe_b"; | |
| reg = <0x00 0x15811000 0x00 0x1000>; | |
| }; | |
| i2c@11e01000 { | |
| clock-names = "main\0dma"; | |
| clock-div = <0x01>; | |
| compatible = "mediatek,mt6983-i2c"; | |
| reg = <0x00 0x11e01000 0x00 0x1000 0x00 0x10217100 0x00 0x80>; | |
| clocks = <0x38 0x01 0x2b 0x3d>; | |
| phandle = <0x15c>; | |
| interrupts = <0x00 0x91 0x04 0x00>; | |
| }; | |
| disp_dsc_wrap0@14012000 { | |
| compatible = "mediatek,disp_dsc_wrap\0mediatek,mt6789-disp-dsc"; | |
| reg = <0x00 0x14012000 0x00 0x1000>; | |
| clocks = <0x35 0x0b>; | |
| phandle = <0x18a>; | |
| interrupts = <0x00 0x12c 0x04 0x00>; | |
| }; | |
| seninf3@1a006000 { | |
| compatible = "mediatek,seninf3"; | |
| reg = <0x00 0x1a006000 0x00 0x1000>; | |
| }; | |
| sleep_sram@1001e000 { | |
| compatible = "mediatek,sleep_sram"; | |
| reg = <0x00 0x1001e000 0x00 0x4000>; | |
| }; | |
| dip_a4@15025000 { | |
| compatible = "mediatek,dip_a4"; | |
| reg = <0x00 0x15025000 0x00 0x1000>; | |
| }; | |
| mcusys_ao_cfg@0c530000 { | |
| reg = <0x00 0xc520100 0x00 0x10000>; | |
| phandle = <0x3d>; | |
| }; | |
| ccifdriver@10209000 { | |
| clock-names = "infra-ccif-ap\0infra-ccif-md\0infra-ccif1-ap\0infra-ccif1-md\0infra-ccif4-md\0infra-ccif5-md"; | |
| compatible = "mediatek,ccci_ccif"; | |
| mediatek,sram_size = <0x200>; | |
| reg = <0x00 0x10209000 0x00 0x1000 0x00 0x1020a000 0x00 0x1000>; | |
| clocks = <0x2b 0x1e 0x2b 0x21 0x2b 0x19 0x2b 0x1a 0x2b 0x39 0x2b 0x33>; | |
| phandle = <0x148>; | |
| interrupts = <0x00 0xe2 0x04 0x00 0x00 0xe3 0x04 0x00>; | |
| }; | |
| mt6789-afe-pcm@11210000 { | |
| pinctrl-6 = <0x70>; | |
| clock-names = "aud_afe_clk\0aud_dac_clk\0aud_dac_predis_clk\0aud_adc_clk\0aud_apll22m_clk\0aud_apll24m_clk\0aud_apll1_tuner_clk\0aud_apll2_tuner_clk\0aud_tml_clk\0aud_nle\0aud_dac_hires_clk\0aud_adc_hires_clk\0aud_adc_hires_tml\0aud_i2s1_bclk\0aud_i2s2_bclk\0aud_i2s3_bclk\0aud_i2s4_bclk\0aud_general3_asrc\0aud_connsys_i2s_asrc\0aud_general1_asrc\0aud_general2_asrc\0aud_infra_clk\0aud_infra_26m_clk\0aud_clk_apmixed_apll1\0aud_clk_apmixed_apll2\0top_mux_audio\0top_mux_audio_int\0top_mainpll_d4_d4\0top_mux_aud_1\0top_apll1_ck\0top_mux_aud_2\0top_apll2_ck\0top_mux_aud_eng1\0top_apll1_d4\0top_apll1_d8\0top_mux_aud_eng2\0top_apll2_d4\0top_apll2_d8\0top_i2s0_m_sel\0top_i2s1_m_sel\0top_i2s2_m_sel\0top_i2s3_m_sel\0top_i2s4_m_sel\0top_i2s5_m_sel\0top_apll12_div0\0top_apll12_div1\0top_apll12_div2\0top_apll12_div3\0top_apll12_div4\0top_apll12_divb\0top_apll12_div5\0top_mux_audio_h\0top_clk26m_clk"; | |
| pinctrl-15 = <0x79>; | |
| pinctrl-11 = <0x75>; | |
| pinctrl-14 = <0x78>; | |
| pinctrl-5 = <0x6f>; | |
| pinctrl-12 = <0x76>; | |
| compatible = "mediatek,mt6789-sound"; | |
| pinctrl-8 = <0x72>; | |
| pinctrl-1 = <0x6b>; | |
| pinctrl-names = "aud_clk_mosi_off\0aud_clk_mosi_on\0aud_clk_miso_off\0aud_clk_miso_on\0aud_dat_mosi_off\0aud_dat_mosi_on\0aud_dat_miso0_off\0aud_dat_miso0_on\0aud_dat_miso1_off\0aud_dat_miso1_on\0aud_gpio_i2s0_off\0aud_gpio_i2s0_on\0aud_gpio_i2s3_off\0aud_gpio_i2s3_on\0vow_dat_miso_off\0vow_dat_miso_on\0vow_clk_miso_off\0vow_clk_miso_on"; | |
| pinctrl-2 = <0x6c>; | |
| pinctrl-16 = <0x7a>; | |
| pinctrl-13 = <0x77>; | |
| apmixedsys = <0x3b>; | |
| pinctrl-7 = <0x71>; | |
| infracfg = <0x2b>; | |
| reg = <0x00 0x11210000 0x00 0x2000>; | |
| clocks = <0x39 0x00 0x39 0x06 0x39 0x07 0x39 0x05 0x39 0x01 0x39 0x02 0x39 0x04 0x39 0x03 0x39 0x08 0x39 0x09 0x39 0x12 0x39 0x13 0x39 0x14 0x39 0x0a 0x39 0x0b 0x39 0x0c 0x39 0x0d 0x39 0x0e 0x39 0x0f 0x39 0x10 0x39 0x11 0x2b 0x20 0x2b 0x25 0x3b 0x0b 0x3b 0x0c 0x2a 0x16 0x2a 0x17 0x2a 0x4d 0x2a 0x28 0x2a 0x6e 0x2a 0x29 0x2a 0x72 0x2a 0x24 0x2a 0x70 0x2a 0x71 0x2a 0x25 0x2a 0x74 0x2a 0x75 0x2a 0x35 0x2a 0x36 0x2a 0x37 0x2a 0x38 0x2a 0x39 0x2a 0x3a 0x2a 0x3f 0x2a 0x40 0x2a 0x41 0x2a 0x42 0x2a 0x43 0x2a 0x44 0x2a 0x45 0x2a 0x2f 0x2a 0x82>; | |
| phandle = <0x7c>; | |
| pinctrl-17 = <0x7b>; | |
| pinctrl-10 = <0x74>; | |
| pinctrl-4 = <0x6e>; | |
| pinctrl-0 = <0x6a>; | |
| topckgen = <0x2a>; | |
| power-domains = <0x2d 0x0b>; | |
| pinctrl-9 = <0x73>; | |
| interrupts = <0x00 0xea 0x04 0x00>; | |
| pinctrl-3 = <0x6d>; | |
| }; | |
| smi_pd_cam_rawb { | |
| mediatek,comm-port-range = <0x08>; | |
| compatible = "mediatek,smi-pd"; | |
| mediatek,smi = <0xa0>; | |
| power-reset = <0x1a06f00c 0x00>; | |
| phandle = <0x17b>; | |
| power-domains = <0x2d 0x0e>; | |
| }; | |
| lkg@00114400 { | |
| compatible = "mediatek,mtk-lkg"; | |
| reg = <0x00 0x114400 0x00 0xc00>; | |
| phandle = <0x113>; | |
| }; | |
| mdp_rsz1@1f009000 { | |
| clock-names = "MDP_RSZ1"; | |
| compatible = "mediatek,mdp_rsz1"; | |
| reg = <0x00 0x1f009000 0x00 0x1000>; | |
| clocks = <0x2c 0x0b>; | |
| phandle = <0xb1>; | |
| }; | |
| mdp_hdr0@1f007000 { | |
| clock-names = "MDP_HDR0"; | |
| compatible = "mediatek,mdp_hdr0"; | |
| reg = <0x00 0x1f007000 0x00 0x1000>; | |
| clocks = <0x2c 0x08>; | |
| phandle = <0xb6>; | |
| }; | |
| infra_dpmaif@1022c000 { | |
| compatible = "mediatek,infra_dpmaif"; | |
| reg = <0x00 0x1022c000 0x00 0x1000>; | |
| }; | |
| extcon_usb { | |
| tcpc = "type_c_port0"; | |
| vbus-voltage = <0x4c4b40>; | |
| mediatek,u2; | |
| vbus-current = <0x1b7740>; | |
| compatible = "mediatek,extcon-usb"; | |
| mediatek,bypss-typec-sink = <0x01>; | |
| vbus-supply = <0xba>; | |
| phandle = <0x197>; | |
| charger = <0x53>; | |
| port { | |
| endpoint@0 { | |
| remote-endpoint = <0xbb>; | |
| phandle = <0xbe>; | |
| }; | |
| }; | |
| }; | |
| mtkfb@0 { | |
| compatible = "mediatek,mtkfb"; | |
| pinctrl-1 = <0x1ce>; | |
| pinctrl-names = "lcm_led_en1_gpio\0lcm_led_en0_gpio\0lcm_rst_out1_gpio\0lcm_rst_out0_gpio\0mode_te_te"; | |
| status = "okay"; | |
| pinctrl-2 = <0x1cf>; | |
| phandle = <0x17c>; | |
| pinctrl-4 = <0x1d1>; | |
| pinctrl-0 = <0x1cd>; | |
| pinctrl-3 = <0x1d0>; | |
| }; | |
| mtee_svp { | |
| compatible = "medaitek,svp"; | |
| phandle = <0x19e>; | |
| }; | |
| md_ccif1@1020c000 { | |
| compatible = "mediatek,md_ccif1"; | |
| reg = <0x00 0x1020c000 0x00 0x1000>; | |
| }; | |
| disp_smi_2x1_sub_comm0@1401b000 { | |
| clock-names = "apb\0smi\0gals0\0gals1"; | |
| mediatek,common-id = <0x01>; | |
| compatible = "mediatek,mt6789-smi-common\0mediatek,smi-common\0syscon\0mediatek,smi-sub-common"; | |
| reg = <0x00 0x1401b000 0x00 0x1000>; | |
| clocks = <0x35 0x0a 0x35 0x0f 0x35 0x13 0x35 0x14>; | |
| phandle = <0x9c>; | |
| power-domains = <0x2d 0x0a>; | |
| init-power-on; | |
| }; | |
| gpio_usage_mapping { | |
| GPIO_FDD_BAND_SUPPORT_DETECT_1ST_PIN = <0x49 0x6f 0x00>; | |
| GPIO_SIM2_HOT_PLUG = <0x49 0x18 0x00>; | |
| compatible = "mediatek,gpio_usage_mapping"; | |
| GPIO_SIM1_SRST = <0x49 0x4e 0x00>; | |
| GPIO_SIM1_SCLK = <0x49 0x4d 0x00>; | |
| GPIO_SIM2_SIO = <0x49 0x52 0x00>; | |
| GPIO_SIM1_SIO = <0x49 0x4f 0x00>; | |
| phandle = <0x14b>; | |
| GPIO_SIM2_SRST = <0x49 0x51 0x00>; | |
| GPIO_SIM1_HOT_PLUG = <0x49 0x17 0x00>; | |
| GPIO_SIM2_SCLK = <0x49 0x50 0x00>; | |
| }; | |
| dfd@13e00000 { | |
| compatible = "mediatek,dfd"; | |
| reg = <0x00 0x13e00000 0x00 0x112000>; | |
| }; | |
| smi_larb17@1a010000 { | |
| clock-names = "apb\0smi"; | |
| compatible = "mediatek,smi_larb17\0mediatek,mt6789-smi-larb\0mediatek,smi-larb"; | |
| mediatek,smi = <0xa0>; | |
| mediatek,larb-id = <0x11>; | |
| reg = <0x00 0x1a010000 0x00 0x1000>; | |
| clocks = <0x2f 0x00 0x2f 0x01>; | |
| phandle = <0x46>; | |
| power-domains = <0x2d 0x0e>; | |
| }; | |
| reserved@1401d000 { | |
| compatible = "mediatek,reserved"; | |
| reg = <0x00 0x1401d000 0x00 0x1000>; | |
| }; | |
| infra_dpmaif@1022e000 { | |
| compatible = "mediatek,infra_dpmaif"; | |
| reg = <0x00 0x1022e000 0x00 0x1000>; | |
| }; | |
| i2c@11015000 { | |
| clock-names = "main\0dma"; | |
| clock-div = <0x01>; | |
| compatible = "mediatek,mt6983-i2c"; | |
| reg = <0x00 0x11015000 0x00 0x1000 0x00 0x10217280 0x00 0x80>; | |
| clocks = <0x3a 0x00 0x2b 0x3d>; | |
| phandle = <0x15e>; | |
| interrupts = <0x00 0x93 0x04 0x00>; | |
| st21nfc@08 { | |
| clkreq-gpios = <0x49 0x44 0x00>; | |
| compatible = "st,st21nfc"; | |
| irq-gpios = <0x49 0x01 0x00>; | |
| status = "ok"; | |
| reset-gpios = <0x49 0x96 0x00>; | |
| interrupt-parent = <0x49>; | |
| reg = <0x08>; | |
| phandle = <0x1fc>; | |
| interrupts = <0x01 0x08 0x01 0x00>; | |
| }; | |
| }; | |
| ap_ccif5@1025c000 { | |
| compatible = "mediatek,ap_ccif5"; | |
| reg = <0x00 0x1025c000 0x00 0x1000>; | |
| }; | |
| imgsys2_config@15820000 { | |
| compatible = "mediatek,imgsys2_config"; | |
| reg = <0x00 0x15820000 0x00 0x1000>; | |
| }; | |
| i2c@11017000 { | |
| clock-names = "main\0dma"; | |
| clock-div = <0x01>; | |
| compatible = "mediatek,mt6983-i2c"; | |
| reg = <0x00 0x11017000 0x00 0x1000 0x00 0x10217400 0x00 0x80>; | |
| clocks = <0x3a 0x01 0x2b 0x3d>; | |
| phandle = <0x160>; | |
| clock-frequency = <0xf4240>; | |
| interrupts = <0x00 0x95 0x04 0x00>; | |
| rt5133@18 { | |
| gpio-controller; | |
| regulator_nb = "rt5133-ldo1\0rt5133-ldo2\0rt5133-ldo3\0rt5133-ldo4\0rt5133-ldo5\0rt5133-ldo6\0rt5133-ldo7\0rt5133-ldo8"; | |
| compatible = "richtek,rt5133"; | |
| #gpio-cells = <0x02>; | |
| gpio-supply = <0x65>; | |
| status = "ok"; | |
| reg = <0x18>; | |
| phandle = <0xb9>; | |
| wakeup-source; | |
| interrupts-extended = <0x49 0x05 0x00>; | |
| enable-gpio = <0x49 0x0f 0x00>; | |
| regulators { | |
| LDO6 { | |
| regulator-min-microvolt = <0x19f0a0>; | |
| oc_ptsel = <0x01>; | |
| pgb_ptsel = <0x01>; | |
| regulator-active-discharge; | |
| phandle = <0x167>; | |
| soft_start_time_sel = <0x01>; | |
| regulator-max-microvolt = <0x2dc6c0>; | |
| regulator-name = "rt5133-ldo6"; | |
| }; | |
| LDO7 { | |
| regulator-min-microvolt = <0xdbba0>; | |
| oc_ptsel = <0x01>; | |
| pgb_ptsel = <0x01>; | |
| regulator-active-discharge; | |
| phandle = <0x168>; | |
| soft_start_time_sel = <0x01>; | |
| regulator-max-microvolt = <0x124f80>; | |
| regulator-name = "rt5133-ldo7"; | |
| }; | |
| LDO3 { | |
| regulator-min-microvolt = <0x19f0a0>; | |
| oc_ptsel = <0x01>; | |
| pgb_ptsel = <0x01>; | |
| regulator-active-discharge; | |
| phandle = <0x164>; | |
| soft_start_time_sel = <0x01>; | |
| regulator-max-microvolt = <0x2dc6c0>; | |
| regulator-name = "rt5133-ldo3"; | |
| }; | |
| BASE { | |
| oc_shutdown_all = <0x00>; | |
| pgb_shutdown_all = <0x00>; | |
| regulator-name = "rt5133,base"; | |
| }; | |
| LDO4 { | |
| regulator-min-microvolt = <0x19f0a0>; | |
| oc_ptsel = <0x01>; | |
| pgb_ptsel = <0x01>; | |
| regulator-active-discharge; | |
| phandle = <0x165>; | |
| soft_start_time_sel = <0x01>; | |
| regulator-max-microvolt = <0x2dc6c0>; | |
| regulator-name = "rt5133-ldo4"; | |
| }; | |
| LDO1 { | |
| regulator-min-microvolt = <0x1b7740>; | |
| oc_ptsel = <0x01>; | |
| pgb_ptsel = <0x01>; | |
| regulator-active-discharge; | |
| phandle = <0x65>; | |
| soft_start_time_sel = <0x01>; | |
| regulator-max-microvolt = <0x1b7740>; | |
| regulator-name = "rt5133-ldo1"; | |
| }; | |
| LDO2 { | |
| regulator-min-microvolt = <0x1b7740>; | |
| oc_ptsel = <0x01>; | |
| pgb_ptsel = <0x01>; | |
| regulator-active-discharge; | |
| phandle = <0x163>; | |
| soft_start_time_sel = <0x01>; | |
| regulator-max-microvolt = <0x30d400>; | |
| regulator-name = "rt5133-ldo2"; | |
| }; | |
| LDO5 { | |
| regulator-min-microvolt = <0x19f0a0>; | |
| oc_ptsel = <0x01>; | |
| pgb_ptsel = <0x01>; | |
| regulator-active-discharge; | |
| phandle = <0x166>; | |
| soft_start_time_sel = <0x01>; | |
| regulator-max-microvolt = <0x2dc6c0>; | |
| regulator-name = "rt5133-ldo5"; | |
| }; | |
| LDO8 { | |
| regulator-min-microvolt = <0xdbba0>; | |
| oc_ptsel = <0x01>; | |
| pgb_ptsel = <0x01>; | |
| regulator-active-discharge; | |
| phandle = <0x169>; | |
| soft_start_time_sel = <0x01>; | |
| regulator-max-microvolt = <0x124f80>; | |
| regulator-name = "rt5133-ldo8"; | |
| }; | |
| }; | |
| }; | |
| mt6375@34 { | |
| compatible = "mediatek,mt6375"; | |
| #interrupt-cells = <0x01>; | |
| status = "okay"; | |
| interrupt-parent = <0x49>; | |
| reg = <0x34>; | |
| phandle = <0x161>; | |
| wakeup-source; | |
| interrupt-controller; | |
| interrupts = <0x04 0x08>; | |
| tcpc { | |
| tcpc,en_wd_sbu_polling; | |
| tcpc,role_def = <0x05>; | |
| wd,sbu_aud_ubound = <0x640>; | |
| wd,sbu_ph_auddev = <0x64>; | |
| tcpc,vconn_supply = <0x01>; | |
| wd,sbu_ph_ubound2_c2c = <0xed8>; | |
| tcpc,en_typec_otp; | |
| boot_mode = <0x50>; | |
| compatible = "mediatek,mt6375-tcpc"; | |
| wd,sbu_ph_lbound = <0x378>; | |
| wd,sbu_ph_lbound1_c2c = <0xb22>; | |
| wd,sbu_pl_lbound_c2c = <0x44c>; | |
| io-channels = <0x61 0x0e 0x61 0x0f>; | |
| wd,sbu_pl_ubound_c2c = <0xa28>; | |
| wd,sbu_calib_init = <0x4b0>; | |
| wd,sbu_pl_bound = <0xc8>; | |
| phandle = <0x162>; | |
| interrupt-names = "pd_evt"; | |
| tcpc,en_ctd; | |
| tcpc,en_wd_polling_only; | |
| tcpc,rp_level = <0x00>; | |
| tcpc,notifier_supply_num = <0x03>; | |
| wd,sbu_ph_ubound1_c2c = <0xc4e>; | |
| tcpc,name = "type_c_port0"; | |
| interrupts = <0x78>; | |
| tcpc,en_wd; | |
| tcpc,en_fod; | |
| charger = <0x53>; | |
| pd-data { | |
| pd,source-cap-ext = <0x637529cf 0x00 0x00 0x00 0x00 0x7010000>; | |
| bat,nr = <0x01>; | |
| pd,pid = <0x6375>; | |
| pd,charging_policy = <0x21>; | |
| pd,id-vdo-data = <0xec0029cf 0x00 0x10000 0x11000001>; | |
| pd,country_nr = <0x00>; | |
| pd,mfrs = "RichtekTCPC"; | |
| pd,vid = <0x29cf>; | |
| pd,sink-pdo-size = <0x02>; | |
| pd,source-pdo-size = <0x01>; | |
| pd,source-pdo-data = <0x19032>; | |
| pd,id-vdo-size = <0x04>; | |
| pd,sink-pdo-data = <0x190c8 0x190c8>; | |
| bat-info0 { | |
| bat,vid = <0x29cf>; | |
| bat,mfrs = "bat1"; | |
| bat,design_cap = <0xbb8>; | |
| bat,pid = <0x6375>; | |
| }; | |
| }; | |
| displayport { | |
| signal,dp_v13; | |
| typec,receptacle; | |
| 2nd_connection = "dfp_d"; | |
| usbr20_not_used; | |
| 1st_connection = "dfp_d"; | |
| dfp_d { | |
| pin_assignment,mode_c; | |
| pin_assignment,mode_d; | |
| pin_assignment,mode_e; | |
| pin_assignment,mode_f; | |
| }; | |
| ufp_d { | |
| }; | |
| }; | |
| dpm_caps { | |
| local_no_suspend; | |
| local_dr_power; | |
| local_vconn_supply; | |
| attempt_enter_dp_mode; | |
| local_dr_data; | |
| attempt_discover_id; | |
| attempt_discover_cable; | |
| pr_check = <0x00>; | |
| dr_check = <0x00>; | |
| local_usb_comm; | |
| }; | |
| }; | |
| chg { | |
| cv = <0x1068>; | |
| phys = <0x63 0x03>; | |
| dcdt_sel = <0x258>; | |
| mivr = <0x1130>; | |
| te_en; | |
| ircmp_r = <0x413c>; | |
| boot_mode = <0x50>; | |
| ircmp_v = <0x20>; | |
| compatible = "mediatek,mt6375-chg"; | |
| vrec = <0x64>; | |
| aicr = <0x1f4>; | |
| chg_name = "primary_chg"; | |
| bc12_sel = <0x62>; | |
| io-channels = <0x61 0x01 0x61 0x03 0x61 0x04 0x61 0x05 0x61 0x06 0x61 0x08 0x61 0x02 0x61 0x07>; | |
| ieoc = <0xfa>; | |
| wdt = <0x9c40>; | |
| phy-names = "usb2-phy"; | |
| vbus_ov = <0x38a4>; | |
| phandle = <0x53>; | |
| interrupt-names = "fl_pwr_rdy\0fl_detach\0fl_vbus_ov\0fl_chg_tout\0fl_wdt\0fl_bc12_dn\0fl_aicc_done\0fl_pe_done\0fl_batpro_done\0adc_vbat_mon_ov"; | |
| usb = <0x64>; | |
| chg_tmr_en; | |
| interrupts = <0x00 0x01 0x08 0x0b 0x17 0x1f 0x12 0x13 0x1b 0x2b>; | |
| otg_lbp = <0xaf0>; | |
| ichg = <0x7d0>; | |
| chg_tmr = <0x0a>; | |
| otg { | |
| regulator-min-microvolt = <0x4a0150>; | |
| regulator-min-microamp = <0x7a120>; | |
| regulator-compatible = "mt6375,otg-vbus"; | |
| phandle = <0xba>; | |
| regulator-max-microamp = <0x249f00>; | |
| regulator-max-microvolt = <0x53ec60>; | |
| regulator-name = "usb-otg-vbus"; | |
| }; | |
| }; | |
| adc { | |
| compatible = "mediatek,mt6375-adc"; | |
| phandle = <0x61>; | |
| interrupt-names = "adc_donei"; | |
| #io-channel-cells = <0x01>; | |
| interrupts = <0x2c>; | |
| }; | |
| dbg { | |
| compatible = "mediatek,mt6375-dbg"; | |
| }; | |
| }; | |
| }; | |
| m4u@10220000 { | |
| compatible = "mediatek,m4u"; | |
| reg = <0x00 0x10220000 0x00 0x2000>; | |
| }; | |
| serial@11002000 { | |
| clock-names = "baud\0bus"; | |
| compatible = "mediatek,mt6577-uart"; | |
| reg = <0x00 0x11002000 0x00 0x1000>; | |
| clocks = <0x55 0x2b 0x0d>; | |
| phandle = <0x159>; | |
| dma-names = "tx\0rx"; | |
| interrupts = <0x00 0x8d 0x04 0x00>; | |
| dmas = <0x60 0x00 0x60 0x01>; | |
| }; | |
| emi_mpu@10226000 { | |
| compatible = "mediatek,emi_mpu"; | |
| reg = <0x00 0x10226000 0x00 0x1000>; | |
| }; | |
| imgsys_config@15020000 { | |
| clock-names = "DIP_CG_IMG_LARB9\0DIP_CG_IMG_DIP"; | |
| iommus = <0x43 0x20120 0x43 0x20121 0x43 0x20122 0x43 0x20123 0x43 0x20124 0x43 0x20125 0x43 0x20126 0x43 0x20127 0x43 0x20128 0x43 0x20129 0x43 0x2012a 0x43 0x2012b 0x43 0x2012c 0x43 0x2012d 0x43 0x2012e>; | |
| mediatek,larb = <0x98>; | |
| compatible = "mediatek,imgsys\0syscon"; | |
| dma-ranges = <0x02 0x00 0x02 0x00 0x01 0x00>; | |
| reg = <0x00 0x15020000 0x00 0x1000>; | |
| clocks = <0x34 0x00 0x34 0x02>; | |
| phandle = <0x18e>; | |
| power-domains = <0x2d 0x06>; | |
| }; | |
| topckgen@10000000 { | |
| compatible = "mediatek,topckgen"; | |
| reg = <0x00 0x10000000 0x00 0x1000>; | |
| }; | |
| dsu-pmu-0 { | |
| compatible = "arm,dsu-pmu"; | |
| cpus = <0x0c 0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13>; | |
| interrupts = <0x00 0x12 0x04 0x00>; | |
| }; | |
| md_power_o1 { | |
| compatible = "mediatek,md_power_o1\0syscon"; | |
| reg = <0x00 0x10006000 0x00 0x1000>; | |
| phandle = <0x5c>; | |
| }; | |
| disp_ovl0_2l@14006000 { | |
| iommus = <0x43 0x21 0x43 0x20>; | |
| mediatek,larb = <0x94>; | |
| compatible = "mediatek,disp_ovl0_2l\0mediatek,mt6789-disp-ovl"; | |
| interconnect-names = "DDP_COMPONENT_OVL0_2L_qos\0DDP_COMPONENT_OVL0_2L_fbdc_qos\0DDP_COMPONENT_OVL0_2L_hrt_qos"; | |
| mediatek,smi-id = <0x01>; | |
| reg = <0x00 0x14006000 0x00 0x1000>; | |
| clocks = <0x35 0x04>; | |
| phandle = <0x181>; | |
| interconnects = <0xa3 0x40021 0xa3 0x10000 0xa3 0x40021 0xa3 0x10000 0xa3 0x40021 0xa3 0x10000>; | |
| interrupts = <0x00 0x120 0x04 0x00>; | |
| }; | |
| smi_larb7@17010000 { | |
| clock-names = "apb\0smi"; | |
| compatible = "mediatek,smi_larb7\0mediatek,mt6789-smi-larb\0mediatek,smi-larb"; | |
| mediatek,smi = <0x9b>; | |
| mediatek,larb-id = <0x07>; | |
| reg = <0x00 0x17010000 0x00 0x1000>; | |
| clocks = <0x32 0x00 0x32 0x02>; | |
| phandle = <0x97>; | |
| power-domains = <0x2d 0x09>; | |
| }; | |
| bus_parity { | |
| infra-names = "MCU2EMI_M0\0MCU2EMI_M1\0MCU2SUBEMI_M0\0MCU2SUBEMI_M1\0MCU2IFR\0IFR_L3C2MCU"; | |
| mcu-names = "MST_CCI_M0\0MST_CCI_M1\0MST_INTAXI_\0SLV_1TO2\0SLV_L3C\0SLV_GIC"; | |
| mcu-types = <0x00 0x00 0x00 0x01 0x01 0x01>; | |
| compatible = "mediatek,bus-parity"; | |
| reg = <0x00 0xc538800 0x00 0x20 0x00 0xc538820 0x00 0x20 0x00 0xc538840 0x00 0x20 0x00 0xc538860 0x00 0x40 0x00 0xc5388a0 0x00 0x30 0x00 0xc5388d0 0x00 0x30 0x00 0x10270600 0x00 0x14 0x00 0x10270620 0x00 0x14 0x00 0x1030e600 0x00 0x14 0x00 0x1030e620 0x00 0x14 0x00 0x100017a8 0x00 0x14 0x00 0x100017bc 0x00 0x08 0x00 0xc53a39c 0x00 0x04>; | |
| interrupt-names = "mcu-bus-parity\0infra-bus-parity"; | |
| infra-types = <0x02 0x02 0x02 0x02 0x01 0x00>; | |
| mcu-data-len = <0x04 0x04 0x02 0x04 0x02 0x02>; | |
| interrupts = <0x00 0x1f 0x04 0x00 0x00 0xd1 0x04 0x00>; | |
| }; | |
| md_ccif3@1023f000 { | |
| compatible = "mediatek,md_ccif3"; | |
| reg = <0x00 0x1023f000 0x00 0x1000>; | |
| }; | |
| aes_top0@10016000 { | |
| compatible = "mediatek,aes_top0"; | |
| reg = <0x00 0x10016000 0x00 0x1000>; | |
| }; | |
| dsi_te { | |
| compatible = "mediatek, dsi_te-eint"; | |
| status = "okay"; | |
| interrupt-parent = <0x49>; | |
| phandle = <0x18c>; | |
| interrupts = <0x53 0x01>; | |
| }; | |
| mtk_iommu_test0 { | |
| iommus = <0x43 0x00>; | |
| compatible = "mediatek,iommu-test-dom0"; | |
| dma-ranges = <0x00 0x00 0x00 0x00 0x04 0x00>; | |
| }; | |
| smi_pd_cam_main { | |
| mediatek,comm-port-range = <0x04 0x08>; | |
| compatible = "mediatek,smi-pd"; | |
| mediatek,smi = <0x9f 0xa0>; | |
| phandle = <0x179>; | |
| main-power; | |
| power-domains = <0x2d 0x0c>; | |
| }; | |
| g3d_config@13fbd000 { | |
| compatible = "mediatek,g3d_config"; | |
| reg = <0x00 0x13fbd000 0x00 0x1000>; | |
| }; | |
| gpufreq_wrapper { | |
| gpufreq-version = <0x02>; | |
| compatible = "mediatek,gpufreq_wrapper"; | |
| dual-buck = <0x00>; | |
| phandle = <0x91>; | |
| gpueb-support = <0x00>; | |
| }; | |
| lvts@1100B000 { | |
| clock-names = "lvts_clk"; | |
| compatible = "mediatek,mt6789-lvts"; | |
| resets = <0x7e 0x00>; | |
| #thermal-sensor-cells = <0x01>; | |
| nvmem-cell-names = "e_data1\0e_data2"; | |
| nvmem-cells = <0x7f 0x80>; | |
| reg = <0x00 0x1100b000 0x00 0x1000>; | |
| clocks = <0x2b 0x04>; | |
| phandle = <0x1b>; | |
| interrupts = <0x00 0xc9 0x04 0x00>; | |
| }; | |
| dxcc_sec@10210000 { | |
| compatible = "mediatek,dxcc_sec"; | |
| reg = <0x00 0x10210000 0x00 0x1000>; | |
| interrupts = <0x00 0xf0 0x04 0x00>; | |
| }; | |
| iommu_test { | |
| iommus = <0x43 0x00>; | |
| compatible = "mediatek,ktf-iommu-test"; | |
| }; | |
| dip_a6@15027000 { | |
| compatible = "mediatek,dip_a6"; | |
| reg = <0x00 0x15027000 0x00 0x1000>; | |
| }; | |
| ged { | |
| gpufreq-supply = <0x92>; | |
| compatible = "mediatek,ged"; | |
| phandle = <0x8b>; | |
| }; | |
| wifi@18000000 { | |
| emi-alignment = <0x1000000>; | |
| memory-region = <0x1fe>; | |
| compatible = "mediatek,wifi"; | |
| reg = <0x00 0x18000000 0x00 0x100000>; | |
| phandle = <0x19f>; | |
| emi-addr = <0x00>; | |
| emi-size = <0x600000>; | |
| emi-max-addr = <0xc0000000>; | |
| interrupts = <0x00 0x199 0x04 0x00>; | |
| }; | |
| md_auxadc { | |
| io-channel-names = "md-channel"; | |
| compatible = "mediatek,md_auxadc"; | |
| io-channels = <0x18 0x02>; | |
| phandle = <0x14a>; | |
| }; | |
| scp@10500000 { | |
| debug_dumptimeout = "enable"; | |
| scp_mem_key = "mediatek,reserve-memory-scp_share"; | |
| core_0 = "enable"; | |
| send_table = <0x00 0x00 0x09 0x03 0x01 0x02 0x04 0x01 0x01 0x05 0x01 0x02 0x06 0x01 0x01 0x1a 0x01 0x09 0x1d 0x02 0x10 0x1f 0x02 0x07 0x29 0x02 0x02 0x0e 0x03 0x01 0x0f 0x03 0x02 0x10 0x03 0x01 0x11 0x03 0x06 0x12 0x03 0x02>; | |
| secure_dump = "enable"; | |
| compatible = "mediatek,scp"; | |
| status = "okay"; | |
| recv_table = <0x01 0x00 0x02 0x00 0x02 0x00 0x1a 0x00 0x07 0x01 0x02 0x00 0x08 0x01 0x0a 0x00 0x09 0x01 0x01 0x00 0x0a 0x01 0x02 0x00 0x1b 0x01 0x02 0x00 0x1c 0x01 0x05 0x00 0x05 0x01 0x01 0x01 0x1e 0x02 0x02 0x00 0x20 0x02 0x07 0x00 0x2a 0x02 0x08 0x00 0x14 0x03 0x0a 0x00 0x15 0x03 0x06 0x00 0x16 0x03 0x01 0x00 0x17 0x03 0x02 0x00 0x0f 0x03 0x01 0x01>; | |
| scp_sramSize = <0xc0000>; | |
| memorydump = <0xc0000 0x3c000 0x3c00 0x400 0x100000>; | |
| mbox_count = <0x04>; | |
| reg = <0x00 0x10500000 0x00 0xc0000 0x00 0x10724000 0x00 0x1000 0x00 0x10721000 0x00 0x1000 0x00 0x10730000 0x00 0x3000 0x00 0x10740000 0x00 0x1000 0x00 0x10752000 0x00 0x1000 0x00 0x10760000 0x00 0x40000 0x00 0x107a5000 0x00 0x04 0x00 0x107fb000 0x00 0x100 0x00 0x107fb100 0x00 0x04 0x00 0x107fb10c 0x00 0x04 0x00 0x107a5020 0x00 0x04 0x00 0x107fc000 0x00 0x100 0x00 0x107fc100 0x00 0x04 0x00 0x107fc10c 0x00 0x04 0x00 0x107a5024 0x00 0x04 0x00 0x107fd000 0x00 0x100 0x00 0x107fd100 0x00 0x04 0x00 0x107fd10c 0x00 0x04 0x00 0x107a5028 0x00 0x04 0x00 0x107fe000 0x00 0x100 0x00 0x107fe100 0x00 0x04 0x00 0x107fe10c 0x00 0x04 0x00 0x107a502c 0x00 0x04 0x00 0x107ff000 0x00 0x100 0x00 0x107ff100 0x00 0x04 0x00 0x107ff10c 0x00 0x04 0x00 0x107a5030 0x00 0x04>; | |
| scp_feature_tbl = <0x00 0x05 0x01 0x01 0x00 0x00 0x02 0x1a 0x00 0x03 0x00 0x00 0x04 0xc8 0x01 0x05 0x00 0x00 0x06 0x78 0x01 0x07 0x0a 0x01 0x08 0x50 0x01 0x09 0x2b 0x01 0x0a 0x16 0x01 0x0b 0x14 0x01 0x0c 0x87 0x01 0x0d 0xc8 0x00 0x0e 0x64 0x00>; | |
| interrupt-names = "ipc0\0ipc1\0mbox0\0mbox1\0mbox2\0mbox3\0mbox4"; | |
| scp_mem_tbl = <0x00 0x00 0x00 0x01 0x4e300 0x00 0x02 0x100000 0x00 0x03 0x180000 0x00 0x04 0x200000 0x00 0x05 0x5a00 0x00 0x06 0x100 0x00 0x07 0x19000 0x00 0x08 0x10000 0x00 0x09 0x1000 0x00 0x0a 0x2000 0x00 0x0b 0x100 0x00 0x0c 0x100 0x00 0x0d 0x19000 0x00>; | |
| reg-names = "scp_sram_base\0scp_cfgreg\0scp_clkreg\0scp_cfgreg_core0\0scp_cfgreg_core1\0scp_bus_tracker\0scp_l1creg\0scp_cfgreg_sec\0mbox0_base\0mbox0_set\0mbox0_clr\0mbox0_init\0mbox1_base\0mbox1_set\0mbox1_clr\0mbox1_init\0mbox2_base\0mbox2_set\0mbox2_clr\0mbox2_init\0mbox3_base\0mbox3_set\0mbox3_clr\0mbox3_init\0mbox4_base\0mbox4_set\0mbox4_clr\0mbox4_init"; | |
| twohart = <0x01>; | |
| interrupts = <0x00 0x1d2 0x04 0x00 0x00 0x1d3 0x04 0x00 0x00 0x1d4 0x04 0x00 0x00 0x1d5 0x04 0x00 0x00 0x1d6 0x04 0x00 0x00 0x1d7 0x04 0x00 0x00 0x1d8 0x04 0x00>; | |
| secure_dump_size = <0x200000>; | |
| core_nums = <0x01>; | |
| }; | |
| mfb@15012000 { | |
| compatible = "mediatek,mfb"; | |
| reg = <0x00 0x15012000 0x00 0x1000>; | |
| }; | |
| gce@10228000 { | |
| clock-names = "gce\0gce-timer"; | |
| #gce-event-cells = <0x01>; | |
| #mbox-cells = <0x03>; | |
| default_tokens = [02 bc 02 bd 02 be 02 bf 02 c0 02 c6 02 c7]; | |
| compatible = "mediatek,mt6789-gce"; | |
| mboxes = <0x66 0x0e 0xffffffff 0x01>; | |
| cpr-not-support-cookie; | |
| reg = <0x00 0x10228000 0x00 0x4000>; | |
| clocks = <0x2b 0x02 0x2b 0x11>; | |
| phandle = <0x66>; | |
| #gce-subsys-cells = <0x02>; | |
| interrupts = <0x00 0xeb 0x04 0x00>; | |
| }; | |
| img0_smi_2x1_sub_comm@1502f000 { | |
| clock-names = "apb\0smi\0gals0\0gals1"; | |
| mediatek,common-id = <0x04>; | |
| compatible = "mediatek,mt6789-smi-common\0syscon\0mediatek,smi-common\0mediatek,smi-sub-common"; | |
| mediatek,smi = <0x9e>; | |
| reg = <0x00 0x1502f000 0x00 0x1000>; | |
| clocks = <0x34 0x00 0x34 0x01 0x34 0x02 0x34 0x03>; | |
| phandle = <0xa1>; | |
| power-domains = <0x2d 0x06>; | |
| }; | |
| apdma@10217000 { | |
| compatible = "mediatek,apdma"; | |
| reg = <0x00 0x10217000 0x00 0x1000>; | |
| }; | |
| usb0@11200000 { | |
| phys = <0x63 0x03>; | |
| clock-names = "sys_clk\0ref_clk\0src_clk"; | |
| infracg = <0xbd>; | |
| mode = <0x02>; | |
| compatible = "mediatek,mt6789-usb20"; | |
| dr_mode = "otg"; | |
| usb-role-switch; | |
| reg = <0x00 0x11200000 0x00 0x10000 0x00 0x11f40000 0x00 0x10000>; | |
| clocks = <0x2b 0x22 0x2a 0x1d 0x3b 0x0d>; | |
| phandle = <0x64>; | |
| interrupt-names = "mc"; | |
| wakeup-source; | |
| pericfg = <0xbc>; | |
| num_eps = <0x10>; | |
| interrupts = <0x00 0x80 0x04 0x00>; | |
| multipoint = <0x01>; | |
| port { | |
| endpoint@0 { | |
| remote-endpoint = <0xbe>; | |
| phandle = <0xbb>; | |
| }; | |
| }; | |
| }; | |
| dip_a9@1502a000 { | |
| compatible = "mediatek,dip_a9"; | |
| reg = <0x00 0x1502a000 0x00 0x1000>; | |
| }; | |
| sys_cirq@10204000 { | |
| compatible = "mediatek,sys_cirq"; | |
| reg = <0x00 0x10204000 0x00 0x1000>; | |
| interrupts = <0x00 0x216 0x04 0x00>; | |
| }; | |
| sound { | |
| compatible = "mediatek,mt6789-mt6366-sound"; | |
| mediatek,platform = <0x7c>; | |
| mediatek,spk-i2s = <0x03 0x00>; | |
| mediatek,scp-audio = <0x7d>; | |
| phandle = <0x175>; | |
| mediatek,speaker-codec { | |
| }; | |
| }; | |
| mfb_b@15810000 { | |
| compatible = "mediatek,mfb_b"; | |
| reg = <0x00 0x15810000 0x00 0x1000>; | |
| }; | |
| devapc@10207000 { | |
| compatible = "mediatek,mt6789-devapc"; | |
| reg = <0x00 0x10207000 0x00 0x1000 0x00 0x10274000 0x00 0x1000 0x00 0x10275000 0x00 0x1000 0x00 0x11020000 0x00 0x1000 0x00 0x10030000 0x00 0x1000 0x00 0x1020e000 0x00 0x1000 0x00 0x10033000 0x00 0x1000 0x00 0x10c000 0x00 0x1000>; | |
| interrupts = <0x00 0xdb 0x04 0x00>; | |
| }; | |
| scp_infra@10001000 { | |
| compatible = "mediatek,scpinfra"; | |
| reg = <0x00 0x10001000 0x00 0x1000>; | |
| phandle = <0x170>; | |
| #clock-cells = <0x01>; | |
| }; | |
| emiisu { | |
| ver_addr = <0x00 0x11d86c>; | |
| buf_addr = <0x00 0x00>; | |
| compatible = "mediatek,common-emiisu"; | |
| ctrl_intf = <0x01>; | |
| buf_size = <0x800000>; | |
| con_addr = <0x00 0x11d858>; | |
| }; | |
| vcp@1ec00000 { | |
| compatible = "mediatek,vcp"; | |
| status = "okay"; | |
| vcp-support = <0x00>; | |
| phandle = <0x190>; | |
| }; | |
| mtk_iommu_debug { | |
| compatible = "mediatek,mt6789-iommu-debug"; | |
| }; | |
| infra_device_mpu@1021b000 { | |
| compatible = "mediatek,infra_device_mpu"; | |
| reg = <0x00 0x1021b000 0x00 0x1000>; | |
| }; | |
| infra_dpmaif@1022f000 { | |
| compatible = "mediatek,infra_dpmaif"; | |
| reg = <0x00 0x1022f000 0x00 0x1000>; | |
| }; | |
| pwrap_mpu@10026000 { | |
| compatible = "mediatek,pwrap_mpu"; | |
| reg = <0x00 0x10026000 0x00 0x1000>; | |
| }; | |
| device_mpu_low@1021a000 { | |
| prot-base = <0x00 0x40000000>; | |
| compatible = "mediatek,device_mpu_low"; | |
| reg = <0x00 0x1021a000 0x00 0x1000>; | |
| page-size = <0x200000>; | |
| prot-size = <0x04 0x00>; | |
| interrupts = <0x00 0xdc 0x04 0x00>; | |
| }; | |
| emichn@10245000 { | |
| compatible = "mediatek,common-emichn"; | |
| reg = <0x00 0x10245000 0x00 0x1000 0x00 0x10235000 0x00 0x1000>; | |
| phandle = <0x4b>; | |
| }; | |
| dip_a7@15028000 { | |
| compatible = "mediatek,dip_a7"; | |
| reg = <0x00 0x15028000 0x00 0x1000>; | |
| }; | |
| vdec_fmt@16080000 { | |
| clock-names = "MT_CG_VDEC\0MT_CG_MINI_MDP"; | |
| iommus = <0x43 0x1008c 0x43 0x1008d>; | |
| rdma0_sw_rst_done_eng = [00 10]; | |
| gce-gpr = <0x0a>; | |
| operating-points-v2 = <0xa9>; | |
| wdma0_tile_done = [00 13]; | |
| m4u-ports = <0x1008c 0x1008d>; | |
| rdma0_tile_done = [00 11]; | |
| mediatek,fmtname = "vdec-fmt"; | |
| rdma1_tile_done = [00 17]; | |
| compatible = "mediatek-vdec-fmt"; | |
| mboxes = <0x66 0x0d 0x7d0 0x01>; | |
| wdma1_tile_done = [00 18]; | |
| dma-ranges = <0x01 0x00 0x01 0x00 0x01 0x00>; | |
| interconnect-names = "path_mini_mdp_r0\0path_mini_mdp_w0"; | |
| reg = <0x00 0x16080000 0x00 0x1000 0x00 0x16081000 0x00 0x1000 0x00 0x1602f000 0x00 0x10000>; | |
| dvfsrc-vcore-supply = <0x42>; | |
| clocks = <0x33 0x05 0x33 0x04>; | |
| wdma0_sw_rst_done_eng = [00 12]; | |
| phandle = <0x18f>; | |
| mediatek,fmt_gce_th_num = <0x01>; | |
| interconnects = <0xa3 0x4008c 0xa3 0x10000 0xa3 0x4008d 0xa3 0x10000>; | |
| rdma1_sw_rst_done_eng = [00 14]; | |
| wdma1_sw_rst_done_eng = [00 16]; | |
| power-domains = <0x2d 0x08>; | |
| mediatek,larbs = <0x96>; | |
| }; | |
| irtx_pwm { | |
| pwm-supply = "vio28"; | |
| pwm_data_invert = <0x00>; | |
| compatible = "mediatek,irtx-pwm"; | |
| phandle = <0x151>; | |
| pwm_ch = <0x01>; | |
| }; | |
| mdp_mutex@1f001000 { | |
| clock-names = "MDP_MUTEX0"; | |
| compatible = "mediatek,mdp_mutex"; | |
| reg = <0x00 0x1f001000 0x00 0x1000>; | |
| clocks = <0x2c 0x09>; | |
| phandle = <0xae>; | |
| }; | |
| i2c@11e00000 { | |
| clock-names = "main\0dma"; | |
| pinctrl-5 = <0x1e0>; | |
| clock-div = <0x01>; | |
| compatible = "mediatek,mt6983-i2c"; | |
| pinctrl-1 = <0x1dc>; | |
| pinctrl-names = "default\0ts_int_active\0ts_reset_active\0ts_int_suspend\0ts_reset_suspend\0ts_i2c_mode"; | |
| pinctrl-2 = <0x1dd>; | |
| reg = <0x00 0x11e00000 0x00 0x1000 0x00 0x10217080 0x00 0x80>; | |
| clocks = <0x38 0x00 0x2b 0x3d>; | |
| phandle = <0x15b>; | |
| pinctrl-4 = <0x1df>; | |
| pinctrl-0 = <0x1db>; | |
| clock-frequency = <0x61a80>; | |
| interrupts = <0x00 0x90 0x04 0x00>; | |
| pinctrl-3 = <0x1de>; | |
| silead_ts@40 { | |
| use_virtual_key = <0x00>; | |
| screen_max_x = <0x438>; | |
| y_axis_mirror = <0x01>; | |
| max_fingers = <0x0a>; | |
| product_name = "silts_3670_AA"; | |
| compatible = "silead,silead_ts"; | |
| x_axis_mirror = <0x01>; | |
| irq-gpios = <0x49 0x09 0x00>; | |
| status = "okay"; | |
| reset-gpios = <0x49 0x98 0x00>; | |
| reg = <0x40>; | |
| screen_max_y = <0x780>; | |
| }; | |
| gt9886@5d { | |
| goodix,input-max-x = <0x438>; | |
| goodix,panel-key-map = <0x9e 0xac 0xd9>; | |
| goodix,firmware-version = "6877v01"; | |
| goodix,reset-gpio = <0x49 0x98 0x00>; | |
| goodix,irq-gpio = <0x49 0x09 0x00>; | |
| goodix,pen-enable; | |
| tpd-filter-enable = <0x00>; | |
| goodix,panel-max-id = <0x0a>; | |
| compatible = "goodix,gt9886"; | |
| goodix,panel-max-y = <0x8e8>; | |
| goodix,panel-max-w = <0x100>; | |
| goodix,config-version = "6877v01"; | |
| goodix,power-off-delay-us = <0x1388>; | |
| status = "ok"; | |
| tpd-filter-custom-speed = <0x00 0x00 0x00>; | |
| goodix,irq-flags = <0x02>; | |
| goodix,input-max-y = <0x8e8>; | |
| interrupt-parent = <0x49>; | |
| reg = <0x5d>; | |
| goodix,panel-max-p = <0x100>; | |
| tpd-filter-custom-prameters = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>; | |
| goodix,key-of-pen = <0x14b 0x14c>; | |
| goodix,power-on-delay-us = <0x2710>; | |
| interrupts = <0x09 0x02 0x09 0x00>; | |
| goodix,panel-max-x = <0x438>; | |
| vtouch-supply = <0x135>; | |
| tpd-filter-pixel-density = <0xa1>; | |
| }; | |
| }; | |
| usb-phy@11f40000 { | |
| #size-cells = <0x02>; | |
| compatible = "mediatek,generic-tphy-v2"; | |
| status = "okay"; | |
| ranges; | |
| #address-cells = <0x02>; | |
| phandle = <0x198>; | |
| usb-phy@11f40000 { | |
| clock-names = "ref"; | |
| mediatek,eye-vrt = <0x04>; | |
| #phy-cells = <0x01>; | |
| nvmem-cell-names = "intr_cal"; | |
| status = "okay"; | |
| mediatek,rx_sqth = <0x05>; | |
| nvmem-cells = <0xbf>; | |
| reg = <0x00 0x11f40000 0x00 0x700>; | |
| mediatek,rev4 = <0x01>; | |
| clocks = <0x55>; | |
| phandle = <0x63>; | |
| mediatek,eye-term = <0x04>; | |
| nvmem-cell-masks = <0x1f>; | |
| mediatek,discth = <0x07>; | |
| }; | |
| }; | |
| fingerprint { | |
| compatible = "mediatek,goodix-fp"; | |
| phandle = <0x158>; | |
| }; | |
| modem_temp_share@10018000 { | |
| compatible = "mediatek,modem_temp_share"; | |
| reg = <0x00 0x10018000 0x00 0x1000>; | |
| }; | |
| eas_info { | |
| csram-base = <0x11bc00>; | |
| compatible = "mediatek,eas-info"; | |
| offs-thermal-limit = <0x1208 0x120c 0x1210>; | |
| offs-cap = <0xfa0>; | |
| phandle = <0x112>; | |
| }; | |
| dip_a5@15026000 { | |
| compatible = "mediatek,dip_a5"; | |
| reg = <0x00 0x15026000 0x00 0x1000>; | |
| }; | |
| topmisc@10011000 { | |
| compatible = "mediatek,topmisc"; | |
| reg = <0x00 0x10011000 0x00 0x1000>; | |
| }; | |
| mmc@11240000 { | |
| clock-names = "source\0hclk\0source_cg"; | |
| bus-width = <0x04>; | |
| vqmmc-supply = <0x89>; | |
| ocr-voltage = <0x30000>; | |
| compatible = "mediatek,mt6789-mmc"; | |
| max-frequency = <0xbebc200>; | |
| req-vcore = <0x9eb10>; | |
| pinctrl-1 = <0x86>; | |
| pinctrl-names = "default\0state_uhs\0pull_down"; | |
| status = "okay"; | |
| pinctrl-2 = <0x87>; | |
| sd-uhs-sdr50; | |
| reg = <0x00 0x11240000 0x00 0x1000 0x00 0x11ef0000 0x00 0x1000>; | |
| dvfsrc-vcore-supply = <0x42>; | |
| clocks = <0x2a 0x15 0x2b 0x15 0x2b 0x1c>; | |
| phandle = <0x178>; | |
| no-mmc; | |
| vmmc-supply = <0x88>; | |
| sd-uhs-sdr25; | |
| pinctrl-0 = <0x85>; | |
| cd-inverted; | |
| cd-debounce-delay-ms = <0x00>; | |
| sd-uhs-sdr12; | |
| cd-gpios = <0x49 0x07 0x01>; | |
| interrupts = <0x00 0x87 0x04 0x00>; | |
| sd-uhs-sdr104; | |
| sd-uhs-ddr50; | |
| cap-sd-highspeed; | |
| host-index = <0x01>; | |
| }; | |
| jpgenc@17030000 { | |
| clock-names = "jpgenc"; | |
| iommus = <0x43 0x100e9 0x43 0x100ea 0x43 0x100eb 0x43 0x100ec>; | |
| operating-points-v2 = <0xaa>; | |
| mediatek,larb = <0x97>; | |
| compatible = "mediatek,mtk-jpgenc-32bit"; | |
| dma-ranges = <0x01 0x00 0x01 0x00 0x01 0x00>; | |
| interconnect-names = "path_jpegenc_y_rdma\0path_jpegenc_c_rmda\0path_jpegenc_q_table\0path_jpegenc_bsdma"; | |
| reg = <0x00 0x17030000 0x00 0x10000>; | |
| dvfsrc-vcore-supply = <0x42>; | |
| clocks = <0x32 0x02>; | |
| interconnects = <0xa3 0x400e9 0xa3 0x10000 0xa3 0x400ea 0xa3 0x10000 0xa3 0x400eb 0xa3 0x10000 0xa3 0x400ec 0xa3 0x10000>; | |
| power-domains = <0x2d 0x09>; | |
| interrupts = <0x00 0x157 0x04 0x00>; | |
| }; | |
| mdp_wrot0@1f00a000 { | |
| clock-names = "MDP_WROT0"; | |
| compatible = "mediatek,mdp_wrot0"; | |
| reg = <0x00 0x1f00a000 0x00 0x1000>; | |
| clocks = <0x2c 0x06>; | |
| phandle = <0xb2>; | |
| }; | |
| smi_disp_comm@14002000 { | |
| clock-names = "apb\0smi\0gals0\0gals1"; | |
| operating-points-v2 = <0x47>; | |
| mediatek,common-id = <0x00>; | |
| compatible = "mediatek,mt6789-smi-common\0syscon\0mediatek,smi-common"; | |
| mediatek,smi = <0x9c 0x9d>; | |
| reg = <0x00 0x14002000 0x00 0x1000>; | |
| clocks = <0x35 0x0a 0x35 0x0f 0x35 0x13 0x35 0x14>; | |
| phandle = <0x9b>; | |
| smi-common; | |
| power-domains = <0x2d 0x0a>; | |
| }; | |
| vow_pmic_efuse { | |
| nvmem-names = "vow_efuse_device"; | |
| nvmem = <0x4d>; | |
| compatible = "mediatek,vow-efuse"; | |
| ver_reg = <0xec>; | |
| ver_mask = <0x1f>; | |
| }; | |
| mdpsys_config@1f000000 { | |
| clock-names = "MDP_IMG_DL_ASYNC0\0MDP_IMG_DL_ASYNC1\0MDP_IMG_DL_RELAY0_ASYNC0\0MDP_IMG_DL_RELAY1_ASYNC1\0MDP_APB_BUS"; | |
| iommus = <0x43 0x20040 0x43 0x20042 0x43 0x20043>; | |
| compatible = "mediatek,mdpsys_config\0syscon"; | |
| dma-ranges = <0x02 0x00 0x02 0x00 0x01 0x00>; | |
| dma_mask_bit = <0x23>; | |
| reg = <0x00 0x1f000000 0x00 0x1000>; | |
| clocks = <0x2c 0x02 0x2c 0x03 0x2c 0x0e 0x2c 0x0f 0x2c 0x05>; | |
| phandle = <0xad>; | |
| }; | |
| mtk_iommu_test2 { | |
| iommus = <0x43 0x20040>; | |
| compatible = "mediatek,iommu-test-dom2"; | |
| dma-ranges = <0x00 0x00 0x00 0x00 0x04 0x00>; | |
| }; | |
| reserved@14010000 { | |
| compatible = "mediatek,reserved"; | |
| reg = <0x00 0x14010000 0x00 0x1000>; | |
| }; | |
| clock_buffer_ctrl { | |
| mediatek,enable; | |
| compatible = "mediatek,clock_buffer_ctrl"; | |
| pmif = <0x54 0x00>; | |
| mediatek,xo-buf-hwbblpm-mask = <0x01 0x00 0x00 0x00 0x00 0x00 0x00>; | |
| phandle = <0x4e>; | |
| mediatek,xo-buf-hwbblpm-bypass = <0x00 0x00 0x00 0x00 0x00 0x00 0x00>; | |
| }; | |
| mbist@17060000 { | |
| compatible = "mediatek,mbist"; | |
| reg = <0x00 0x17060000 0x00 0x10000>; | |
| }; | |
| dip_a0@15021000 { | |
| compatible = "mediatek,dip1"; | |
| reg = <0x00 0x15021000 0x00 0xc000>; | |
| interrupts = <0x00 0x17a 0x04 0x00>; | |
| }; | |
| smi_larb13@1a001000 { | |
| clock-names = "apb\0smi"; | |
| compatible = "mediatek,smi_larb13\0mediatek,mt6789-smi-larb\0mediatek,smi-larb"; | |
| mediatek,smi = <0xa0>; | |
| mediatek,larb-id = <0x0d>; | |
| reg = <0x00 0x1a001000 0x00 0x1000>; | |
| clocks = <0x31 0x00 0x31 0x00>; | |
| phandle = <0x44>; | |
| power-domains = <0x2d 0x0c>; | |
| }; | |
| apmixed@1000c000 { | |
| compatible = "mediatek,apmixed"; | |
| reg = <0x00 0x1000c000 0x00 0xe00>; | |
| }; | |
| disp_aal0@1400c000 { | |
| mtk_aal_support = <0x01>; | |
| compatible = "mediatek,disp_aal0\0mediatek,mt6789-disp-aal"; | |
| mtk_dre30_support = <0x00>; | |
| reg = <0x00 0x1400c000 0x00 0x1000>; | |
| clocks = <0x35 0x07>; | |
| phandle = <0x186>; | |
| interrupts = <0x00 0x126 0x04 0x00>; | |
| }; | |
| serial@11003000 { | |
| clock-names = "baud\0bus"; | |
| compatible = "mediatek,mt6577-uart"; | |
| reg = <0x00 0x11003000 0x00 0x1000>; | |
| clocks = <0x55 0x2b 0x0e>; | |
| phandle = <0x15a>; | |
| dma-names = "tx\0rx"; | |
| interrupts = <0x00 0x8e 0x04 0x00>; | |
| dmas = <0x60 0x02 0x60 0x03>; | |
| }; | |
| disp_dither0@1400f000 { | |
| pure_clr_num = <0x07>; | |
| pure_clr_det = <0x00>; | |
| pure_clr_rgb = <0xff 0x00 0x00 0x00 0xff 0x00 0x00 0x00 0xff 0xff 0xff 0x00 0xff 0x00 0xff 0x00 0xff 0xff 0xff 0xff 0xff>; | |
| compatible = "mediatek,disp_dither0\0mediatek,mt6789-disp-dither"; | |
| reg = <0x00 0x1400f000 0x00 0x1000>; | |
| clocks = <0x35 0x0e>; | |
| phandle = <0x189>; | |
| interrupts = <0x00 0x129 0x04 0x00>; | |
| }; | |
| drm@1000d000 { | |
| compatible = "mediatek,dbgtop-drm"; | |
| rgu_timeout = <0xea60>; | |
| reg = <0x00 0x1000d000 0x00 0x1000>; | |
| phandle = <0x111>; | |
| ver = <0x01>; | |
| }; | |
| scp_gpio@10005000 { | |
| compatible = "mediatek,scp_gpio\0syscon"; | |
| reg = <0x00 0x10005000 0x00 0x1000>; | |
| phandle = <0x58>; | |
| }; | |
| dip_b0@15821000 { | |
| compatible = "mediatek,dip_b0"; | |
| reg = <0x00 0x15821000 0x00 0x1000>; | |
| interrupts = <0x00 0x181 0x04 0x00>; | |
| }; | |
| mdp_aal0@1f005000 { | |
| clock-names = "MDP_AAL0"; | |
| compatible = "mediatek,mdp_aal0"; | |
| reg = <0x00 0x1f005000 0x00 0x1000>; | |
| clocks = <0x2c 0x0d>; | |
| phandle = <0xb5>; | |
| }; | |
| watchdog@10007000 { | |
| compatible = "mediatek,mt6789-wdt\0mediatek,mt6589-wdt\0syscon\0simple-mfd"; | |
| reg = <0x00 0x10007000 0x00 0x100>; | |
| phandle = <0x117>; | |
| reboot-mode { | |
| mode-rpmbpk = <0x08>; | |
| compatible = "syscon-reboot-mode"; | |
| offset = <0x24>; | |
| mask = <0x0f>; | |
| mode-dm-verity-dev-corrupt = <0x04>; | |
| mode-kpoc = <0x05>; | |
| mode-ddr-reserve = <0x06>; | |
| mode-meta = <0x07>; | |
| mode-recovery = <0x02>; | |
| mode-bootloader = <0x03>; | |
| mode-charger = <0x01>; | |
| }; | |
| }; | |
| reserved@1f00e000 { | |
| compatible = "mediatek,reserved"; | |
| reg = <0x00 0x1f00e000 0x00 0x1000>; | |
| }; | |
| mcusys_pll1u_top@1000c000 { | |
| reg = <0x00 0x1000c000 0x00 0x1000>; | |
| phandle = <0x3c>; | |
| }; | |
| spi4@11018000 { | |
| clock-names = "parent-clk\0sel-clk\0spi-clk"; | |
| compatible = "mediatek,mt6789-spi"; | |
| mediatek,pad-select = <0x00>; | |
| reg = <0x00 0x11018000 0x00 0x100>; | |
| clocks = <0x2a 0x7f 0x2a 0x12 0x2b 0x2c>; | |
| phandle = <0x156>; | |
| interrupts = <0x00 0xc3 0x04 0x00>; | |
| }; | |
| infracfg_ao_mem@10002000 { | |
| compatible = "mediatek,infracfg_ao_mem"; | |
| reg = <0x00 0x10002000 0x00 0x1000>; | |
| }; | |
| snd_scp_ultra { | |
| compatible = "mediatek,snd_scp_ultra"; | |
| scp_ultra_dl_memif_id = <0x07>; | |
| scp_ultra_ul_memif_id = <0x0e>; | |
| phandle = <0x173>; | |
| }; | |
| ap_ccif1@1020b000 { | |
| compatible = "mediatek,ap_ccif1"; | |
| reg = <0x00 0x1020b000 0x00 0x1000>; | |
| }; | |
| vcu@16000000 { | |
| iommus = <0x43 0x10080 0x43 0x10081 0x43 0x10082 0x43 0x10083 0x43 0x10084 0x43 0x10085 0x43 0x10086 0x43 0x10087 0x43 0x10088 0x43 0x10089 0x43 0x1008b 0x43 0x1008a>; | |
| gce-gpr = <0x0a 0x0b>; | |
| mediatek,vcuid = <0x00>; | |
| compatible = "mediatek-vcu"; | |
| mboxes = <0x66 0x07 0x00 0x01 0x66 0x0c 0x00 0x01 0x66 0x17 0x00 0x01 0x68 0x0c 0x00 0x01>; | |
| mediatek,dec_gce_th_num = <0x01>; | |
| mediatek,vcuname = "vcu"; | |
| mediatek,vcu-off = <0x00>; | |
| gce_sec_token = [02 b9]; | |
| dma-ranges = <0x01 0x00 0x01 0x00 0x01 0x00>; | |
| mediatek,enc_gce_th_num = <0x02>; | |
| gce-events = <0x66 0x81 0x66 0x82 0x66 0x84 0x66 0x89 0x66 0x88 0x66 0x85 0x66 0x00 0x66 0x01 0x66 0x02 0x66 0x03 0x66 0x04 0x66 0x05 0x66 0x06 0x66 0x07 0x66 0x08 0x66 0x09 0x66 0x0a 0x66 0x0b 0x66 0x0f>; | |
| gce_norm_token = [02 b8]; | |
| reg = <0x00 0x16000000 0x00 0x40000 0x00 0x17020000 0x00 0x10000 0x00 0x17820000 0x00 0x10000>; | |
| gce-event-names = "venc_eof\0venc_cmdq_pause_done\0venc_mb_done\0venc_sps_done\0venc_pps_done\0venc_128B_cnt_done\0vdec_pic_start\0vdec_decode_done\0vdec_pause\0vdec_dec_error\0vdec_mc_busy_overflow_timeout\0vdec_all_dram_req_done\0vdec_ini_fetch_rdy\0vdec_process_flag\0vdec_search_start_code_done\0vdec_ref_reorder_done\0vdec_wp_tble_done\0vdec_count_sram_clr_done\0vdec_gce_cnt_op_threshold"; | |
| phandle = <0xac>; | |
| mediatek,iommu-padding; | |
| }; | |
| auxadc@11001000 { | |
| clock-names = "main"; | |
| nvmem-names = "mtk_efuse"; | |
| nvmem = <0x69>; | |
| compatible = "mediatek,mt6765-auxadc"; | |
| #interconnect-cells = <0x01>; | |
| mediatek,cali-oe-bit = <0x00>; | |
| mediatek,cali-efuse-reg-offset = <0x198>; | |
| reg = <0x00 0x11001000 0x00 0x1000>; | |
| clocks = <0x2b 0x17>; | |
| phandle = <0x18>; | |
| mediatek,cali-en-bit = <0x14>; | |
| #io-channel-cells = <0x01>; | |
| mediatek,cali-ge-bit = <0x0a>; | |
| interrupts = <0x00 0x60 0x01 0x00>; | |
| }; | |
| pwraphal@10026000 { | |
| compatible = "mediatek,pwraph"; | |
| mediatek,pwrap-regmap = <0x54>; | |
| phandle = <0x146>; | |
| }; | |
| dip_b11@1582c000 { | |
| compatible = "mediatek,dip_b11"; | |
| reg = <0x00 0x1582c000 0x00 0x1000>; | |
| }; | |
| dfd_mcu@0c530000 { | |
| enabled = <0x01>; | |
| check_pattern_offset = <0x00>; | |
| buf_addr_align = <0x1000000>; | |
| sw_version = <0x01>; | |
| compatible = "mediatek,dfd_mcu"; | |
| dfd_disable_efuse = <0xffffffff 0xffffffff>; | |
| nr_max_core = <0x08>; | |
| nr_big_core = <0x02>; | |
| buf_length = <0x100000>; | |
| dfd_timeout = <0x1f4>; | |
| chip_id_offset = <0x18>; | |
| nr_header_row = <0x00>; | |
| phandle = <0x10f>; | |
| nr_rs_entry_little = <0x06>; | |
| hw_version = <0x1e>; | |
| nr_rs_entry_big = <0x02>; | |
| dfd_cache { | |
| enabled = <0x00>; | |
| tap_en = <0x43ff>; | |
| buf_length = <0x800000>; | |
| dfd_timeout = <0x2710>; | |
| phandle = <0x110>; | |
| }; | |
| }; | |
| disp_rsz0@14008000 { | |
| compatible = "mediatek,disp_rsz0\0mediatek,mt6789-disp-rsz"; | |
| reg = <0x00 0x14008000 0x00 0x1000>; | |
| clocks = <0x35 0x06>; | |
| phandle = <0x183>; | |
| interrupts = <0x00 0x122 0x04 0x00>; | |
| }; | |
| dip_b1@15822000 { | |
| compatible = "mediatek,dip_b1"; | |
| reg = <0x00 0x15822000 0x00 0x1000>; | |
| }; | |
| dbg_tracker2@10218000 { | |
| compatible = "mediatek,dbg_tracker2"; | |
| reg = <0x00 0x10218000 0x00 0x1000>; | |
| }; | |
| trng@1020f000 { | |
| compatible = "mediatek,trng"; | |
| reg = <0x00 0x1020f000 0x00 0x1000>; | |
| interrupts = <0x00 0xef 0x04 0x00>; | |
| }; | |
| dvfsrc@10012000 { | |
| compatible = "mediatek,mt6789-dvfsrc"; | |
| #interconnect-cells = <0x01>; | |
| reg = <0x00 0x10012000 0x00 0x1000 0x00 0x10006000 0x00 0x1000>; | |
| phandle = <0x22>; | |
| reg-names = "dvfsrc\0spm"; | |
| dvfsrc-vcore { | |
| regulator-min-microvolt = <0x86470>; | |
| regulator-always-on; | |
| phandle = <0x42>; | |
| regulator-max-microvolt = <0xb1008>; | |
| regulator-name = "dvfsrc-vcore"; | |
| }; | |
| dvfsrc-vscp { | |
| regulator-min-microvolt = <0x86470>; | |
| regulator-always-on; | |
| phandle = <0x57>; | |
| regulator-max-microvolt = <0xb1008>; | |
| regulator-name = "dvfsrc-vscp"; | |
| }; | |
| dvfsrc-met { | |
| rc-vcore-supply = <0x42>; | |
| compatible = "mediatek,dvfsrc-met"; | |
| interconnect-names = "icc-bw\0icc-hrt-bw"; | |
| interconnects = <0x22 0x18 0x22 0x00 0x22 0x21 0x22 0x19>; | |
| }; | |
| opp6 { | |
| phandle = <0x29>; | |
| opp-peak-KBps = <0x00>; | |
| }; | |
| opp0 { | |
| phandle = <0x23>; | |
| opp-peak-KBps = <0x9ba3c0>; | |
| }; | |
| opp2 { | |
| phandle = <0x25>; | |
| opp-peak-KBps = <0x5a06e0>; | |
| }; | |
| opp5 { | |
| phandle = <0x28>; | |
| opp-peak-KBps = <0x2625a0>; | |
| }; | |
| opp3 { | |
| phandle = <0x26>; | |
| opp-peak-KBps = <0x4dd1e0>; | |
| }; | |
| dvfsrc-helper { | |
| rc-vcore-supply = <0x42>; | |
| vcore-supply = <0x56>; | |
| compatible = "mediatek,dvfsrc-helper"; | |
| required-opps = <0x23 0x24 0x25 0x26 0x27 0x28>; | |
| rc-vscp-supply = <0x57>; | |
| interconnect-names = "icc-bw\0icc-perf-bw\0icc-hrt-bw"; | |
| interconnects = <0x22 0x18 0x22 0x00 0x22 0x18 0x22 0x00 0x22 0x21 0x22 0x19>; | |
| }; | |
| opp1 { | |
| phandle = <0x24>; | |
| opp-peak-KBps = <0x73f780>; | |
| }; | |
| opp4 { | |
| phandle = <0x27>; | |
| opp-peak-KBps = <0x39fbc0>; | |
| }; | |
| }; | |
| regulator_vibrator { | |
| min-volt = <0x2ab980>; | |
| label = "vibrator"; | |
| compatible = "regulator-vibrator"; | |
| vib-supply = <0x48>; | |
| phandle = <0x115>; | |
| max-volt = <0x3567e0>; | |
| }; | |
| ap_ccif3@1023e000 { | |
| compatible = "mediatek,ap_ccif3"; | |
| reg = <0x00 0x1023e000 0x00 0x1000>; | |
| interrupts = <0x00 0xe7 0x04 0x00>; | |
| }; | |
| seninf1@1a004000 { | |
| compatible = "mediatek,seninf1"; | |
| reg = <0x00 0x1a004000 0x00 0x1000>; | |
| }; | |
| smi_larb4@1602e000 { | |
| clock-names = "apb\0smi"; | |
| compatible = "mediatek,smi_larb4\0mediatek,mt6789-smi-larb\0mediatek,smi-larb"; | |
| mediatek,smi = <0x9b>; | |
| mediatek,larb-id = <0x04>; | |
| reg = <0x00 0x1602e000 0x00 0x1000>; | |
| clocks = <0x33 0x00 0x33 0x05>; | |
| phandle = <0x96>; | |
| power-domains = <0x2d 0x08>; | |
| }; | |
| dip_b3@15824000 { | |
| compatible = "mediatek,dip_b3"; | |
| reg = <0x00 0x15824000 0x00 0x1000>; | |
| }; | |
| reserved@1f004000 { | |
| compatible = "mediatek,reserved"; | |
| reg = <0x00 0x1f004000 0x00 0x1000>; | |
| }; | |
| MD1_SIM1_HOT_PLUG_EINT { | |
| debounce = <0x00 0x2710>; | |
| src_pin = <0x00 0x01>; | |
| compatible = "mediatek,md1_sim1_hot_plug_eint-eint"; | |
| dedicated = <0x00 0x00>; | |
| status = "okay"; | |
| phandle = <0x14c>; | |
| interrupts = <0x00 0x08>; | |
| sockettype = <0x00 0x00>; | |
| }; | |
| rsc@1b003000 { | |
| clock-names = "RSC_CLK_IPE_RSC\0RSC_CLK_IPE_LARB20"; | |
| iommus = <0x43 0x20284 0x43 0x20285>; | |
| mediatek,larb = <0x9a>; | |
| compatible = "mediatek,rsc"; | |
| mboxes = <0x66 0x15 0x00 0x01>; | |
| dma-ranges = <0x02 0x00 0x02 0x00 0x01 0x00>; | |
| gce-events = <0x66 0xb3>; | |
| reg = <0x00 0x1b003000 0x00 0x1000>; | |
| gce-event-names = "rsc_eof"; | |
| clocks = <0x2e 0x05 0x2e 0x01>; | |
| power-domains = <0x2d 0x07>; | |
| interrupts = <0x00 0x188 0x04 0x00>; | |
| }; | |
| spi1@11010000 { | |
| clock-names = "parent-clk\0sel-clk\0spi-clk"; | |
| compatible = "mediatek,mt6789-spi"; | |
| mediatek,pad-select = <0x00>; | |
| reg = <0x00 0x11010000 0x00 0x100>; | |
| clocks = <0x2a 0x7f 0x2a 0x12 0x2b 0x26>; | |
| phandle = <0x153>; | |
| interrupts = <0x00 0xc0 0x04 0x00>; | |
| }; | |
| pericfg@10003000 { | |
| compatible = "mediatek,pericfg\0syscon"; | |
| reg = <0x00 0x10003000 0x00 0x1000>; | |
| phandle = <0xbc>; | |
| }; | |
| disp_rdma0@14007000 { | |
| iommus = <0x43 0x22>; | |
| mediatek,larb = <0x94>; | |
| compatible = "mediatek,disp_rdma0\0mediatek,mt6789-disp-rdma"; | |
| interconnect-names = "DDP_COMPONENT_RDMA0_qos\0DDP_COMPONENT_RDMA0_hrt_qos"; | |
| mediatek,smi-id = <0x01>; | |
| reg = <0x00 0x14007000 0x00 0x1000>; | |
| clocks = <0x35 0x03>; | |
| phandle = <0x182>; | |
| interconnects = <0xa3 0x40022 0xa3 0x10000 0xa3 0x40022 0xa3 0x10000>; | |
| interrupts = <0x00 0x121 0x04 0x00>; | |
| }; | |
| devapc_ao_mm@1001c000 { | |
| compatible = "mediatek,devapc_ao_mm"; | |
| reg = <0x00 0x1001c000 0x00 0x1000>; | |
| }; | |
| smart_pa { | |
| status = "okay"; | |
| interrupt-parent = <0x49>; | |
| phandle = <0x171>; | |
| interrupts = <0x06 0x08>; | |
| }; | |
| venc@17000000 { | |
| clock-names = "MT_CG_VENC0"; | |
| iommus = <0x43 0x100e0 0x43 0x100e1 0x43 0x100e2 0x43 0x100e3 0x43 0x100e4 0x43 0x100e5 0x43 0x100e6 0x43 0x100e7 0x43 0x100e8 0x43 0x100e9 0x43 0x100ea 0x43 0x100eb 0x43 0x100ec>; | |
| operating-points-v2 = <0xaa>; | |
| throughput-normal-max = <0x1b4c8680>; | |
| interconnect-num = <0x0a>; | |
| throughput-op-rate-thresh = <0x78>; | |
| throughput-config-offset = <0x02>; | |
| compatible = "mediatek,mt6789-vcodec-enc"; | |
| mediatek,platform = "platform:mt6789"; | |
| dma-ranges = <0x01 0x00 0x01 0x00 0x01 0x00>; | |
| mediatek,vcu = <0xac>; | |
| bandwidth-table = <0x04 0x0a 0x03 0xa0 0x00 0x14 0x05 0x04 0x05 0x10 0x01 0xc2 0x02 0x61 0x01 0x00 0x02 0x282 0x06 0x07>; | |
| interconnect-names = "path_venc_rcpu\0path_venc_rec\0path_venc_bsdma\0path_venc_sv_comv\0path_venc_rd_comv\0path_venc_cur_luma\0path_venc_cur_chroma\0venc_ref_luma\0path_venc_ref_chroma\0path_larb7"; | |
| throughput-table = <0x34363248 0x04 0x35c 0x587 0x34363248 0x05 0x2fe 0x47f 0x43564548 0x02 0x9b4 0xe77 0x43564548 0x04 0x6f4 0xb49 0x35363248 0x02 0x9b4 0xe77 0x35363248 0x04 0x6f4 0xb49 0x46494548 0x02 0x9b4 0xe77 0x46494548 0x04 0x6f4 0xb49>; | |
| throughput-min = <0xee6b280>; | |
| mediatek,ipm = <0x01>; | |
| reg = <0x00 0x17020000 0x00 0x2000 0x00 0x17820000 0x00 0x20000>; | |
| dvfsrc-vcore-supply = <0x42>; | |
| config-table = <0x34363248 0x3b538 0x04 0x04 0x34363248 0x76a70 0x05 0x05 0x43564548 0x3b538 0x02 0x02 0x43564548 0x76a70 0x04 0x04 0x35363248 0x3b538 0x02 0x02 0x35363248 0x76a70 0x04 0x04 0x46494548 0x3b538 0x02 0x02 0x46494548 0x76a70 0x04 0x04 0x46494548 0xffffffff 0x09 0x07>; | |
| clocks = <0x32 0x01>; | |
| interconnects = <0xa3 0x400e0 0xa3 0x10000 0xa3 0x400e1 0xa3 0x10000 0xa3 0x400e2 0xa3 0x10000 0xa3 0x400e3 0xa3 0x10000 0xa3 0x400e4 0xa3 0x10000 0xa3 0x400e5 0xa3 0x10000 0xa3 0x400e6 0xa3 0x10000 0xa3 0x400e7 0xa3 0x10000 0xa3 0x400e8 0xa3 0x10000 0xa3 0x30007 0xa3 0x10000>; | |
| reg-names = "VENC_SYS\0VENC_C1_SYS"; | |
| mediatek,larbs = <0x97>; | |
| interrupts = <0x00 0x156 0x04 0x00>; | |
| }; | |
| dip_b10@1582b000 { | |
| compatible = "mediatek,dip_b10"; | |
| reg = <0x00 0x1582b000 0x00 0x1000>; | |
| }; | |
| cq_dma@10212000 { | |
| dma-channels = <0x04>; | |
| compatible = "mediatek,mt6765-cqdma"; | |
| reg = <0x00 0x10212000 0x00 0x80 0x00 0x10212100 0x00 0x80 0x00 0x10212200 0x00 0x80 0x00 0x10212300 0x00 0x80>; | |
| dma-channel-mask = <0x3f>; | |
| interrupts = <0x00 0xba 0x04 0x00 0x00 0xbb 0x04 0x00 0x00 0xbc 0x04 0x00 0x00 0xbd 0x04 0x00>; | |
| }; | |
| odm { | |
| compatible = "simple-bus"; | |
| phandle = <0x192>; | |
| leds { | |
| compatible = "gpio-leds"; | |
| red { | |
| label = "red"; | |
| default-state = "off"; | |
| gpios = <0x49 0x56 0x00>; | |
| }; | |
| blue { | |
| label = "blue"; | |
| default-state = "off"; | |
| gpios = <0x49 0x58 0x00>; | |
| }; | |
| green { | |
| label = "green"; | |
| default-state = "off"; | |
| gpios = <0x49 0x57 0x00>; | |
| }; | |
| }; | |
| rt5133-gpio1 { | |
| regulator-min-microvolt = <0x1b7740>; | |
| compatible = "regulator-fixed"; | |
| vin-supply = <0x65>; | |
| enable-active-high; | |
| phandle = <0x194>; | |
| gpio = <0xb9 0x00 0x00>; | |
| regulator-max-microvolt = <0x1b7740>; | |
| regulator-name = "rt5133-gpio1"; | |
| }; | |
| rt5133-gpio3 { | |
| regulator-min-microvolt = <0x1b7740>; | |
| compatible = "regulator-fixed"; | |
| vin-supply = <0x65>; | |
| enable-active-high; | |
| phandle = <0x196>; | |
| gpio = <0xb9 0x02 0x00>; | |
| regulator-max-microvolt = <0x1b7740>; | |
| regulator-name = "rt5133-gpio3"; | |
| }; | |
| rt5133-gpio2 { | |
| regulator-min-microvolt = <0x1b7740>; | |
| compatible = "regulator-fixed"; | |
| vin-supply = <0x65>; | |
| enable-active-high; | |
| phandle = <0x195>; | |
| gpio = <0xb9 0x01 0x00>; | |
| regulator-max-microvolt = <0x1b7740>; | |
| regulator-name = "rt5133-gpio2"; | |
| }; | |
| gpd_fan_control { | |
| compatible = "gpd,fan_control"; | |
| pinctrl-1 = <0x1ef>; | |
| pinctrl-names = "fan_control_set_off\0fan_control_set_on"; | |
| status = "okay"; | |
| phandle = <0x1fb>; | |
| pinctrl-0 = <0x1ee>; | |
| }; | |
| kte-joystick { | |
| compatible = "kte-gpio-keys"; | |
| io-channels = <0x18 0x05 0x18 0x04 0x18 0x03 0x18 0x02>; | |
| keypm-gpios = <0x49 0x45 0x00>; | |
| poll-interval = <0x08>; | |
| joystick-key { | |
| L2 { | |
| label = "L2"; | |
| gpios = <0x49 0x0c 0x01>; | |
| linux,code = <0x138>; | |
| interrupt-parent = <0x49>; | |
| debounce-interval = <0x08>; | |
| interrupts = <0x0c 0x08 0x0c 0x00>; | |
| }; | |
| DU { | |
| label = "DU"; | |
| gpios = <0x49 0x34 0x01>; | |
| linux,code = <0x67>; | |
| interrupt-parent = <0x49>; | |
| debounce-interval = <0x08>; | |
| interrupts = <0x34 0x08 0x34 0x00>; | |
| }; | |
| R3 { | |
| label = "R3"; | |
| gpios = <0x49 0x2b 0x01>; | |
| linux,code = <0x13e>; | |
| interrupt-parent = <0x49>; | |
| debounce-interval = <0x08>; | |
| interrupts = <0x2b 0x08 0x2b 0x00>; | |
| }; | |
| S2 { | |
| label = "S2"; | |
| gpios = <0x49 0x0d 0x01>; | |
| linux,code = <0xac>; | |
| interrupt-parent = <0x49>; | |
| debounce-interval = <0x08>; | |
| interrupts = <0x0d 0x08 0x0d 0x00>; | |
| }; | |
| A4 { | |
| label = "A4"; | |
| gpios = <0x49 0x35 0x01>; | |
| linux,code = <0x134>; | |
| interrupt-parent = <0x49>; | |
| debounce-interval = <0x08>; | |
| interrupts = <0x35 0x08 0x35 0x00>; | |
| }; | |
| DL { | |
| label = "DL"; | |
| gpios = <0x49 0x06 0x01>; | |
| linux,code = <0x69>; | |
| interrupt-parent = <0x49>; | |
| debounce-interval = <0x08>; | |
| interrupts = <0x06 0x08 0x06 0x00>; | |
| }; | |
| L1 { | |
| label = "L1"; | |
| gpios = <0x49 0x0a 0x01>; | |
| linux,code = <0x136>; | |
| interrupt-parent = <0x49>; | |
| debounce-interval = <0x08>; | |
| interrupts = <0x0a 0x08 0x0a 0x00>; | |
| }; | |
| S4 { | |
| label = "S4"; | |
| gpios = <0x49 0x2a 0x01>; | |
| linux,code = <0x13b>; | |
| interrupt-parent = <0x49>; | |
| debounce-interval = <0x08>; | |
| interrupts = <0x2a 0x08 0x2a 0x00>; | |
| }; | |
| A1 { | |
| label = "A1"; | |
| gpios = <0x49 0x30 0x01>; | |
| linux,code = <0x130>; | |
| interrupt-parent = <0x49>; | |
| debounce-interval = <0x08>; | |
| interrupts = <0x30 0x08 0x30 0x00>; | |
| }; | |
| S1 { | |
| label = "S1"; | |
| gpios = <0x49 0x33 0x01>; | |
| linux,code = <0x13a>; | |
| interrupt-parent = <0x49>; | |
| debounce-interval = <0x08>; | |
| interrupts = <0x33 0x08 0x33 0x00>; | |
| }; | |
| DD { | |
| label = "DD"; | |
| gpios = <0x49 0x31 0x01>; | |
| linux,code = <0x6c>; | |
| interrupt-parent = <0x49>; | |
| debounce-interval = <0x08>; | |
| interrupts = <0x31 0x08 0x31 0x00>; | |
| }; | |
| R2 { | |
| label = "R2"; | |
| gpios = <0x49 0x2c 0x01>; | |
| linux,code = <0x139>; | |
| interrupt-parent = <0x49>; | |
| debounce-interval = <0x08>; | |
| interrupts = <0x2c 0x08 0x2c 0x00>; | |
| }; | |
| S3 { | |
| label = "S3"; | |
| gpios = <0x49 0x32 0x01>; | |
| linux,code = <0x8b>; | |
| interrupt-parent = <0x49>; | |
| debounce-interval = <0x08>; | |
| interrupts = <0x32 0x08 0x32 0x00>; | |
| }; | |
| A3 { | |
| label = "A3"; | |
| gpios = <0x49 0x2e 0x01>; | |
| linux,code = <0x133>; | |
| interrupt-parent = <0x49>; | |
| debounce-interval = <0x08>; | |
| interrupts = <0x2e 0x08 0x2e 0x00>; | |
| }; | |
| A2 { | |
| label = "A2"; | |
| gpios = <0x49 0x2f 0x01>; | |
| linux,code = <0x131>; | |
| interrupt-parent = <0x49>; | |
| debounce-interval = <0x08>; | |
| interrupts = <0x2f 0x08 0x2f 0x00>; | |
| }; | |
| L3 { | |
| label = "L3"; | |
| gpios = <0x49 0x1a 0x01>; | |
| linux,code = <0x13d>; | |
| interrupt-parent = <0x49>; | |
| debounce-interval = <0x08>; | |
| interrupts = <0x1a 0x08 0x1a 0x00>; | |
| }; | |
| DR { | |
| label = "DR"; | |
| gpios = <0x49 0x1b 0x01>; | |
| linux,code = <0x6a>; | |
| interrupt-parent = <0x49>; | |
| debounce-interval = <0x08>; | |
| interrupts = <0x1b 0x08 0x1b 0x00>; | |
| }; | |
| R1 { | |
| label = "R1"; | |
| gpios = <0x49 0x2d 0x01>; | |
| linux,code = <0x137>; | |
| interrupt-parent = <0x49>; | |
| debounce-interval = <0x08>; | |
| interrupts = <0x2d 0x08 0x2d 0x00>; | |
| }; | |
| }; | |
| joystick { | |
| axis@0 { | |
| linux,code = <0x00>; | |
| abs-range = <0x00 0xff>; | |
| cali-val = <0x24c 0x80e 0xeef>; | |
| reg = <0x00>; | |
| abs-fuzz = <0x03>; | |
| abs-flat = <0x0f>; | |
| }; | |
| axis@1 { | |
| linux,code = <0x01>; | |
| abs-range = <0x00 0xff>; | |
| cali-val = <0xe20 0x796 0x1e4>; | |
| reg = <0x01>; | |
| abs-fuzz = <0x03>; | |
| abs-flat = <0x0f>; | |
| }; | |
| axis@2 { | |
| linux,code = <0x02>; | |
| abs-range = <0x00 0xff>; | |
| cali-val = <0xce6 0x6e2 0x50>; | |
| reg = <0x02>; | |
| abs-fuzz = <0x03>; | |
| abs-flat = <0x0f>; | |
| }; | |
| axis@3 { | |
| linux,code = <0x05>; | |
| abs-range = <0x00 0xff>; | |
| cali-val = <0x1e1 0x7de 0xd6d>; | |
| reg = <0x03>; | |
| abs-fuzz = <0x03>; | |
| abs-flat = <0x0f>; | |
| }; | |
| }; | |
| }; | |
| rt5133_eint { | |
| status = "okay"; | |
| interrupt-parent = <0x49>; | |
| phandle = <0x193>; | |
| interrupts = <0x05 0x02>; | |
| }; | |
| }; | |
| iommu@1401a000 { | |
| compatible = "mediatek,common-disp-iommu-bank4"; | |
| reg = <0x00 0x1401a000 0x00 0x1000>; | |
| phandle = <0xa8>; | |
| interrupts = <0x00 0x133 0x04 0x00>; | |
| mediatek,bank-id = <0x04>; | |
| }; | |
| iommu@14019000 { | |
| compatible = "mediatek,common-disp-iommu-bank3"; | |
| reg = <0x00 0x14019000 0x00 0x1000>; | |
| phandle = <0xa7>; | |
| interrupts = <0x00 0x132 0x04 0x00>; | |
| mediatek,bank-id = <0x03>; | |
| }; | |
| disp_smi_2x1_sub_comm1@1401c000 { | |
| clock-names = "apb\0smi\0gals0\0gals1"; | |
| mediatek,common-id = <0x02>; | |
| compatible = "mediatek,mt6789-smi-common\0mediatek,smi-common\0syscon\0mediatek,smi-sub-common"; | |
| reg = <0x00 0x1401c000 0x00 0x1000>; | |
| clocks = <0x35 0x0a 0x35 0x0f 0x35 0x13 0x35 0x14>; | |
| phandle = <0x9d>; | |
| power-domains = <0x2d 0x0a>; | |
| }; | |
| sys_cirq@10313000 { | |
| compatible = "mediatek,sys_cirq"; | |
| reg = <0x00 0x10313000 0x00 0x1000>; | |
| }; | |
| dpmaif@10014000 { | |
| clock-names = "infra-dpmaif-clk"; | |
| mediatek,chip_info = <0x1a85>; | |
| compatible = "mediatek,dpmaif"; | |
| reg = <0x00 0x10014000 0x00 0x1000 0x00 0x10014400 0x00 0x1000 0x00 0x1022d000 0x00 0x1000 0x00 0x1022d100 0x00 0x1000 0x00 0x1022d400 0x00 0x1000 0x00 0x1022c000 0x00 0x1000 0x00 0x1022e000 0x00 0x1000>; | |
| clocks = <0x2b 0x37>; | |
| phandle = <0x147>; | |
| interrupts = <0x00 0xf1 0x04 0x00>; | |
| mediatek,dpmaif_ver = <0x01>; | |
| mediatek,dpmaif_capability = <0x06>; | |
| }; | |
| i2c@11eb2000 { | |
| clock-names = "main\0dma"; | |
| clock-div = <0x01>; | |
| #size-cells = <0x00>; | |
| compatible = "mediatek,mt6983-i2c"; | |
| status = "okay"; | |
| #address-cells = <0x01>; | |
| reg = <0x00 0x11eb2000 0x00 0x1000 0x00 0x10217600 0x00 0x80>; | |
| clocks = <0x37 0x02 0x2b 0x3d>; | |
| phandle = <0x16d>; | |
| clock-frequency = <0x61a80>; | |
| interrupts = <0x00 0x98 0x04 0x00>; | |
| camera_main_af@72 { | |
| compatible = "mediatek,camera_main_af"; | |
| status = "okay"; | |
| reg = <0x72>; | |
| phandle = <0x1f7>; | |
| }; | |
| camera_eeprom0@50 { | |
| compatible = "mediatek,camera_eeprom"; | |
| status = "okay"; | |
| reg = <0x50>; | |
| phandle = <0x1f2>; | |
| }; | |
| camera_main@1a { | |
| compatible = "mediatek,camera_main"; | |
| #thermal-sensor-cells = <0x00>; | |
| status = "okay"; | |
| reg = <0x1a>; | |
| phandle = <0x1ca>; | |
| }; | |
| }; | |
| disp_wdma0@14014000 { | |
| iommus = <0x43 0x23>; | |
| mediatek,larb = <0x94>; | |
| compatible = "mediatek,disp_wdma0\0mediatek,mt6789-disp-wdma"; | |
| mediatek,smi-id = <0x01>; | |
| reg = <0x00 0x14014000 0x00 0x1000>; | |
| clocks = <0x35 0x05>; | |
| phandle = <0x18d>; | |
| interrupts = <0x00 0x12e 0x04 0x00>; | |
| }; | |
| g3d_config@13fbc000 { | |
| compatible = "mediatek,g3d_config"; | |
| reg = <0x00 0x13fbc000 0x00 0x1000>; | |
| }; | |
| depth@1b100000 { | |
| compatible = "mediatek,depth"; | |
| reg = <0x00 0x1b100000 0x00 0x1000>; | |
| interrupts = <0x00 0x18a 0x04 0x00>; | |
| }; | |
| }; | |
| syscon@1a000000 { | |
| compatible = "mediatek,mt6789-camsys_main\0syscon"; | |
| reg = <0x00 0x1a000000 0x00 0x1000>; | |
| phandle = <0x31>; | |
| #clock-cells = <0x01>; | |
| }; | |
| cam_mem { | |
| iommus = <0x43 0x20120 0x43 0x20121 0x43 0x20122 0x43 0x20123 0x43 0x20124 0x43 0x20125 0x43 0x20126 0x43 0x20127 0x43 0x20128 0x43 0x20129 0x43 0x2012a 0x43 0x2012b 0x43 0x2012c 0x43 0x2012d 0x43 0x2012e 0x43 0x2012f 0x43 0x20130 0x43 0x20131 0x43 0x20132 0x43 0x20133 0x43 0x20134 0x43 0x20135 0x43 0x20136 0x43 0x20137 0x43 0x20138 0x43 0x20139 0x43 0x201a0 0x43 0x201a1 0x43 0x201a2 0x43 0x201a6 0x43 0x201a7 0x43 0x201a8 0x43 0x20200 0x43 0x20201 0x43 0x20202 0x43 0x20203 0x43 0x20204 0x43 0x20205 0x43 0x20206 0x43 0x20207 0x43 0x20208 0x43 0x20209 0x43 0x2020a 0x43 0x2020b 0x43 0x2020c 0x43 0x2020d 0x43 0x2020e 0x43 0x2020f 0x43 0x20210 0x43 0x20220 0x43 0x20221 0x43 0x20222 0x43 0x20223 0x43 0x20224 0x43 0x20225 0x43 0x20226 0x43 0x20227 0x43 0x20228 0x43 0x20229 0x43 0x2022a 0x43 0x2022b 0x43 0x2022c 0x43 0x2022d 0x43 0x2022e 0x43 0x2022f 0x43 0x20230>; | |
| compatible = "mediatek,cam_mem"; | |
| mediatek,platform = "mt6789"; | |
| dma-ranges = <0x02 0x00 0x02 0x00 0x01 0x00>; | |
| }; | |
| clk_ao { | |
| compatible = "simple-bus"; | |
| phandle = <0xf1>; | |
| }; | |
| ssram1@10450000 { | |
| #size-cells = <0x01>; | |
| compatible = "mmio-sram_1"; | |
| ranges = <0x00 0x00 0x10450000 0x80>; | |
| #address-cells = <0x01>; | |
| reg = <0x00 0x10450000 0x00 0x80>; | |
| tiny_mbox@0 { | |
| compatible = "arm,scmi-tx-shmem"; | |
| reg = <0x00 0x80>; | |
| phandle = <0x15>; | |
| }; | |
| }; | |
| utos { | |
| compatible = "microtrust,utos"; | |
| phandle = <0xec>; | |
| interrupts = <0x00 0x76 0x01 0x00>; | |
| }; | |
| touch_panel { | |
| compatible = "goodix,touch"; | |
| phandle = <0xf8>; | |
| }; | |
| syscon@1a04f000 { | |
| compatible = "mediatek,mt6789-camsys_rawa\0syscon"; | |
| reg = <0x00 0x1a04f000 0x00 0x1000>; | |
| phandle = <0x30>; | |
| #clock-cells = <0x01>; | |
| }; | |
| cam1_legacy@1a030000 { | |
| mediatek,larb = <0x45>; | |
| compatible = "mediatek,cam1_legacy"; | |
| dma-ranges = <0x02 0x00 0x02 0x00 0x01 0x00>; | |
| reg = <0x00 0x1a030000 0x00 0x8000>; | |
| phandle = <0xfa>; | |
| power-domains = <0x2d 0x0d>; | |
| interrupts = <0x00 0x160 0x04 0x00>; | |
| }; | |
| lk_charger { | |
| temp_t1_threshold = <0x00>; | |
| pd_charger_current = <0x7a120>; | |
| compatible = "mediatek,lk_charger"; | |
| fast_charge_voltage = <0x2dc6c0>; | |
| enable_anime; | |
| ac_charger_input_current = <0x30d400>; | |
| temp_t4_threshold = <0x32>; | |
| ac_charger_current = <0x1f47d0>; | |
| usb_charger_current = <0x2dc6c0>; | |
| non_std_ac_charger_current = <0x7a120>; | |
| temp_t3_threshold = <0x2d>; | |
| phandle = <0x1a5>; | |
| power_path_support; | |
| enable_check_vsys; | |
| enable_pd20_reset; | |
| charging_host_charger_current = <0x16e360>; | |
| ta_ac_charger_current = <0x2dc6c0>; | |
| max_charger_voltage = <0x632ea0>; | |
| }; | |
| syscon@1b000000 { | |
| compatible = "mediatek,mt6789-ipesys\0syscon"; | |
| reg = <0x00 0x1b000000 0x00 0x1000>; | |
| phandle = <0x2e>; | |
| #clock-cells = <0x01>; | |
| }; | |
| ssram2@10460000 { | |
| #size-cells = <0x01>; | |
| compatible = "mmio-sram_2"; | |
| ranges = <0x00 0x00 0x10460000 0x80>; | |
| #address-cells = <0x01>; | |
| reg = <0x00 0x10460000 0x00 0x80>; | |
| tiny_mbox@1 { | |
| compatible = "arm,scmi-rx-shmem"; | |
| reg = <0x00 0x80>; | |
| phandle = <0x16>; | |
| }; | |
| }; | |
| opp-table-venc { | |
| compatible = "operating-points-v2"; | |
| phandle = <0xaa>; | |
| opp-0 { | |
| opp-hz = <0x00 0xed77040>; | |
| opp-microvolt = <0x86470>; | |
| }; | |
| opp-1 { | |
| opp-hz = <0x00 0x15b23300>; | |
| opp-microvolt = <0x927c0>; | |
| }; | |
| opp-2 { | |
| opp-hz = <0x00 0x1b4c8680>; | |
| opp-microvolt = <0x9eb10>; | |
| }; | |
| opp-3 { | |
| opp-hz = <0x00 0x25317c00>; | |
| opp-microvolt = <0xb1008>; | |
| }; | |
| }; | |
| swpm { | |
| pmu_dsu_type = <0x09>; | |
| compatible = "mediatek,mtk-swpm"; | |
| pmu_dsu_support = <0x00>; | |
| phandle = <0xd4>; | |
| pmu_boundary_num = <0x06>; | |
| }; | |
| clocks { | |
| clk13m { | |
| compatible = "fixed-clock"; | |
| phandle = <0x5f>; | |
| #clock-cells = <0x00>; | |
| clock-frequency = <0xc65d40>; | |
| }; | |
| ulposc { | |
| compatible = "fixed-clock"; | |
| phandle = <0xf5>; | |
| #clock-cells = <0x00>; | |
| clock-frequency = <0xf7f4900>; | |
| }; | |
| clk32k { | |
| compatible = "fixed-clock"; | |
| phandle = <0xf4>; | |
| #clock-cells = <0x00>; | |
| clock-frequency = <0x7d00>; | |
| }; | |
| clk26m { | |
| compatible = "fixed-clock"; | |
| phandle = <0x55>; | |
| #clock-cells = <0x00>; | |
| clock-frequency = <0x18cba80>; | |
| }; | |
| }; | |
| cpus { | |
| #size-cells = <0x00>; | |
| #address-cells = <0x01>; | |
| cpu@005 { | |
| compatible = "arm,cortex-a55"; | |
| cpu-idle-states = <0x03 0x04 0x05 0x06 0x07 0x08 0x09>; | |
| performance-domains = <0x02 0x00>; | |
| enable-method = "psci"; | |
| capacity-dmips-mhz = <0x17f>; | |
| reg = <0x500>; | |
| phandle = <0x11>; | |
| device_type = "cpu"; | |
| }; | |
| cpu@101 { | |
| compatible = "arm,cortex-a76"; | |
| cpu-idle-states = <0x0a 0x0b 0x05 0x06 0x07 0x08 0x09>; | |
| performance-domains = <0x02 0x01>; | |
| enable-method = "psci"; | |
| capacity-dmips-mhz = <0x400>; | |
| reg = <0x700>; | |
| phandle = <0x13>; | |
| device_type = "cpu"; | |
| }; | |
| cpu@100 { | |
| compatible = "arm,cortex-a76"; | |
| cpu-idle-states = <0x0a 0x0b 0x05 0x06 0x07 0x08 0x09>; | |
| performance-domains = <0x02 0x01>; | |
| enable-method = "psci"; | |
| capacity-dmips-mhz = <0x400>; | |
| reg = <0x600>; | |
| phandle = <0x12>; | |
| device_type = "cpu"; | |
| }; | |
| cpu@000 { | |
| compatible = "arm,cortex-a55"; | |
| cpu-idle-states = <0x03 0x04 0x05 0x06 0x07 0x08 0x09>; | |
| performance-domains = <0x02 0x00>; | |
| enable-method = "psci"; | |
| capacity-dmips-mhz = <0x17f>; | |
| reg = <0x00>; | |
| phandle = <0x0c>; | |
| device_type = "cpu"; | |
| }; | |
| cpu@001 { | |
| compatible = "arm,cortex-a55"; | |
| cpu-idle-states = <0x03 0x04 0x05 0x06 0x07 0x08 0x09>; | |
| performance-domains = <0x02 0x00>; | |
| enable-method = "psci"; | |
| capacity-dmips-mhz = <0x17f>; | |
| reg = <0x100>; | |
| phandle = <0x0d>; | |
| device_type = "cpu"; | |
| }; | |
| idle-states { | |
| entry-method = "arm,psci"; | |
| clusteroff_l { | |
| local-timer-stop; | |
| compatible = "arm,idle-state"; | |
| arm,psci-suspend-param = <0x1010101>; | |
| entry-latency-us = <0x64>; | |
| exit-latency-us = <0xfa>; | |
| phandle = <0x04>; | |
| min-residency-us = <0x834>; | |
| }; | |
| s2idle { | |
| local-timer-stop; | |
| compatible = "arm,idle-state"; | |
| arm,psci-suspend-param = <0x1011f01>; | |
| entry-latency-us = <0x2710>; | |
| exit-latency-us = <0x2710>; | |
| phandle = <0x09>; | |
| min-residency-us = <0xffffffff>; | |
| }; | |
| system_mem { | |
| local-timer-stop; | |
| compatible = "arm,idle-state"; | |
| arm,psci-suspend-param = <0x1010f01>; | |
| entry-latency-us = <0x2bc>; | |
| exit-latency-us = <0x352>; | |
| phandle = <0x06>; | |
| min-residency-us = <0xfa0>; | |
| }; | |
| clusteroff_b { | |
| local-timer-stop; | |
| compatible = "arm,idle-state"; | |
| arm,psci-suspend-param = <0x1010102>; | |
| entry-latency-us = <0x64>; | |
| exit-latency-us = <0xfa>; | |
| phandle = <0x0b>; | |
| min-residency-us = <0x76c>; | |
| }; | |
| mcusysoff { | |
| local-timer-stop; | |
| compatible = "arm,idle-state"; | |
| arm,psci-suspend-param = <0x1010701>; | |
| entry-latency-us = <0x1c2>; | |
| exit-latency-us = <0x258>; | |
| phandle = <0x05>; | |
| min-residency-us = <0xfa0>; | |
| }; | |
| cpuoff_b { | |
| local-timer-stop; | |
| compatible = "arm,idle-state"; | |
| arm,psci-suspend-param = <0x10002>; | |
| entry-latency-us = <0x32>; | |
| exit-latency-us = <0x64>; | |
| phandle = <0x0a>; | |
| min-residency-us = <0x578>; | |
| }; | |
| system_bus { | |
| local-timer-stop; | |
| compatible = "arm,idle-state"; | |
| arm,psci-suspend-param = <0x1010f03>; | |
| entry-latency-us = <0x514>; | |
| exit-latency-us = <0xaf0>; | |
| phandle = <0x08>; | |
| min-residency-us = <0xfa0>; | |
| }; | |
| system_pll { | |
| local-timer-stop; | |
| compatible = "arm,idle-state"; | |
| arm,psci-suspend-param = <0x1010f02>; | |
| entry-latency-us = <0x320>; | |
| exit-latency-us = <0x3b6>; | |
| phandle = <0x07>; | |
| min-residency-us = <0xfa0>; | |
| }; | |
| cpuoff_l { | |
| local-timer-stop; | |
| compatible = "arm,idle-state"; | |
| arm,psci-suspend-param = <0x10001>; | |
| entry-latency-us = <0x32>; | |
| exit-latency-us = <0x64>; | |
| phandle = <0x03>; | |
| min-residency-us = <0x640>; | |
| }; | |
| }; | |
| cpu@002 { | |
| compatible = "arm,cortex-a55"; | |
| cpu-idle-states = <0x03 0x04 0x05 0x06 0x07 0x08 0x09>; | |
| performance-domains = <0x02 0x00>; | |
| enable-method = "psci"; | |
| capacity-dmips-mhz = <0x17f>; | |
| reg = <0x200>; | |
| phandle = <0x0e>; | |
| device_type = "cpu"; | |
| }; | |
| cpu@003 { | |
| compatible = "arm,cortex-a55"; | |
| cpu-idle-states = <0x03 0x04 0x05 0x06 0x07 0x08 0x09>; | |
| performance-domains = <0x02 0x00>; | |
| enable-method = "psci"; | |
| capacity-dmips-mhz = <0x17f>; | |
| reg = <0x300>; | |
| phandle = <0x0f>; | |
| device_type = "cpu"; | |
| }; | |
| cpu-map { | |
| cluster1 { | |
| core1 { | |
| cpu = <0x13>; | |
| }; | |
| core0 { | |
| cpu = <0x12>; | |
| }; | |
| }; | |
| cluster0 { | |
| core1 { | |
| cpu = <0x0d>; | |
| }; | |
| core3 { | |
| cpu = <0x0f>; | |
| }; | |
| core2 { | |
| cpu = <0x0e>; | |
| }; | |
| core5 { | |
| cpu = <0x11>; | |
| }; | |
| core4 { | |
| cpu = <0x10>; | |
| }; | |
| core0 { | |
| cpu = <0x0c>; | |
| }; | |
| }; | |
| }; | |
| cpu@004 { | |
| compatible = "arm,cortex-a55"; | |
| cpu-idle-states = <0x03 0x04 0x05 0x06 0x07 0x08 0x09>; | |
| performance-domains = <0x02 0x00>; | |
| enable-method = "psci"; | |
| capacity-dmips-mhz = <0x17f>; | |
| reg = <0x400>; | |
| phandle = <0x10>; | |
| device_type = "cpu"; | |
| }; | |
| }; | |
| md_power_throttling { | |
| lbat_md_reduce_tx = <0x06>; | |
| compatible = "mediatek,md-power-throttling"; | |
| oc_md_reduce_tx = <0x06>; | |
| phandle = <0x10d>; | |
| }; | |
| opp-table-disp0 { | |
| compatible = "operating-points-v2"; | |
| phandle = <0x47>; | |
| opp-0 { | |
| opp-hz = <0x00 0xc65d400>; | |
| opp-microvolt = <0x86470>; | |
| }; | |
| opp-1 { | |
| opp-hz = <0x00 0x1298be00>; | |
| opp-microvolt = <0x927c0>; | |
| }; | |
| opp-2 { | |
| opp-hz = <0x00 0x18cba800>; | |
| opp-microvolt = <0x9eb10>; | |
| }; | |
| opp-3 { | |
| opp-hz = <0x00 0x208b4c80>; | |
| opp-microvolt = <0xb1008>; | |
| }; | |
| }; | |
| hwrng { | |
| compatible = "arm,sec-rng"; | |
| methods = "smc"; | |
| quality = [03 84]; | |
| phandle = <0xee>; | |
| method-fid = [02 6a]; | |
| }; | |
| camsv6_legacy@1a096000 { | |
| mediatek,larb = <0x44>; | |
| compatible = "mediatek,camsv6_legacy"; | |
| dma-ranges = <0x02 0x00 0x02 0x00 0x01 0x00>; | |
| reg = <0x00 0x1a096000 0x00 0x1000>; | |
| phandle = <0x104>; | |
| interrupts = <0x00 0x16e 0x04 0x00>; | |
| }; | |
| camsv5_legacy@1a095000 { | |
| mediatek,larb = <0x44>; | |
| compatible = "mediatek,camsv5_legacy"; | |
| dma-ranges = <0x02 0x00 0x02 0x00 0x01 0x00>; | |
| reg = <0x00 0x1a095000 0x00 0x1000>; | |
| phandle = <0x103>; | |
| interrupts = <0x00 0x16a 0x04 0x00>; | |
| }; | |
| syscon@10001000 { | |
| compatible = "mediatek,mt6789-infracfg_ao\0syscon\0simple-mfd"; | |
| reg = <0x00 0x10001000 0x00 0x1000>; | |
| phandle = <0x2b>; | |
| #clock-cells = <0x01>; | |
| reset-controller { | |
| compatible = "ti,syscon-reset"; | |
| #reset-cells = <0x01>; | |
| phandle = <0x7e>; | |
| ti,reset-bits = <0x120 0x00 0x124 0x00 0x00 0x00 0x1c 0x130 0x0f 0x134 0x0f 0x00 0x00 0x1c 0x140 0x07 0x144 0x07 0x00 0x00 0x1c 0x150 0x15 0x154 0x15 0x00 0x00 0x1c>; | |
| }; | |
| }; | |
| qos@0011bb00 { | |
| compatible = "mediatek,mt6893-qos"; | |
| mediatek,qos_enable = <0x01>; | |
| reg = <0x00 0x11bb00 0x00 0x100>; | |
| phandle = <0xe8>; | |
| }; | |
| syscon@11E02000 { | |
| compatible = "mediatek,mt6789-imp_iic_wrap_w\0syscon"; | |
| reg = <0x00 0x11e02000 0x00 0x1000>; | |
| phandle = <0x38>; | |
| #clock-cells = <0x01>; | |
| }; | |
| dcm@10001000 { | |
| compatible = "mediatek,mt6789-dcm"; | |
| reg = <0x00 0x10001000 0x00 0x1000 0x00 0x10022000 0x00 0x1000 0x00 0xc530000 0x00 0x5000 0x00 0xc538000 0x00 0x5000 0x00 0xc53a800 0x00 0x1000>; | |
| phandle = <0xf0>; | |
| reg-names = "infracfg_ao\0infra_ao_bcrm\0mcusys_par_wrap\0mp_cpusys_top\0cpccfg_reg"; | |
| }; | |
| syscon@15020000 { | |
| compatible = "mediatek,mt6789-imgsys1\0syscon"; | |
| reg = <0x00 0x15020000 0x00 0x1000>; | |
| phandle = <0x34>; | |
| #clock-cells = <0x01>; | |
| }; | |
| opp-table-cam { | |
| compatible = "operating-points-v2"; | |
| phandle = <0x41>; | |
| opp-0 { | |
| opp-hz = <0x00 0x110c0380>; | |
| opp-microvolt = <0x86470>; | |
| }; | |
| opp-1 { | |
| opp-hz = <0x00 0x175d7200>; | |
| opp-microvolt = <0x927c0>; | |
| }; | |
| opp-2 { | |
| opp-hz = <0x00 0x208b4c80>; | |
| opp-microvolt = <0x9eb10>; | |
| }; | |
| opp-3 { | |
| opp-hz = <0x00 0x25317c00>; | |
| opp-microvolt = <0xb1008>; | |
| }; | |
| }; | |
| interrupt-controller { | |
| #size-cells = <0x02>; | |
| compatible = "arm,gic-v3"; | |
| #interrupt-cells = <0x04>; | |
| #address-cells = <0x02>; | |
| interrupt-parent = <0x01>; | |
| reg = <0x00 0xc000000 0x00 0x40000 0x00 0xc040000 0x00 0x200000>; | |
| phandle = <0x01>; | |
| #redistributor-regions = <0x01>; | |
| interrupt-controller; | |
| interrupts = <0x01 0x09 0x04 0x00>; | |
| }; | |
| memory { | |
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| reg = <0x00 0x40000000 0x01 0x80000000>; | |
| device_type = "memory"; | |
| }; | |
| met { | |
| met_res_ram { | |
| compatible = "mediatek,met_res_ram"; | |
| met_res_ram_mcupm { | |
| start = <0x00>; | |
| size = <0x400000>; | |
| }; | |
| met_res_ram_sspm { | |
| start = <0x00>; | |
| size = <0x400000>; | |
| }; | |
| }; | |
| sspm-rts-header { | |
| node_28 = "SSPM_SWPM_CPU__MCUSYS_STATE_RATIO\0active,idle,off"; | |
| node_58 = "SSPM_SWPM_VPU__VPU0_STATE_RATIO\0active,idle,off"; | |
| node_34 = "SSPM_SWPM_GPU__LOADING\0loading"; | |
| node_31 = "SSPM_SWPM_CPU__LKG_POWER\0cpu0,cpu1,cpu2,cpu3,cpu4,cpu5,cpu6,cpu7,dsu"; | |
| node_68 = "SSPM_SWPM_SOC__SMAP\0i2max,imax"; | |
| node_23 = "SSPM_SWPM_CPU__CORE_PMU_INST_SPEC\0cpu0,cpu1,cpu2,cpu3,cpu4,cpu5,cpu6,cpu7"; | |
| node_57 = "SSPM_SWPM_ME__IDX\0vdec_fps,venc_fps,disp_fps,disp_resolution"; | |
| node_11 = "SSPM_CM_MGR_DE_TIMES\0up0,up1,up2,up3,up4,up5,\0down0,down1,down2,down3,down4,down5,reset"; | |
| node_18 = "SSPM_SWPM_CPU__CORE_ACTIVE_RATIO\0cpu0,cpu1,cpu2,cpu3,cpu4,cpu5,cpu6,cpu7"; | |
| node_54 = "SSPM_SWPM_DRAM__DVFS\0ddr_freq"; | |
| node_1 = "SSPM_MET_UNIT_TEST\0test"; | |
| node_21 = "SSPM_SWPM_CPU__CORE_STALL_RATIO\0cpu0,cpu1,cpu2,cpu3,cpu4,cpu5,cpu6,cpu7"; | |
| node_42 = "SSPM_SWPM_CORE__IPE_STATE_RATIO\0FDVT_active,DVP_active,DVS_active,DV_idle,off"; | |
| node_59 = "SSPM_SWPM_VPU__VPU1_STATE_RATIO\0active,idle,off"; | |
| node_51 = "SSPM_SWPM_CORE__POWER\0dramc,infra_top,aphy_vcore"; | |
| node_13 = "SSPM_CM_MGR_DSU_DVFS_ACT_STALL_PWR\0up_L_a,up_B_a,up_BB_a,cur_L_a,cur_B_a,\0cur_BB_a,down_L_a,down_B_a,down_BB_a,\0up_L_s,up_B_s,up_BB_s,cur_L_s,cur_B_s,\0cur_BB_s,down_L_s,down_B_s,down_BB_s"; | |
| node_52 = "SSPM_SWPM_CORE__LKG_POWER\0infra_top,dramc,thermal"; | |
| node_4 = "SSPM_CM_MGR_LOADING\0ratio,cps"; | |
| node_49 = "SSPM_SWPM_CORE__VDO_CODING_TYPE\0venc,vdec"; | |
| node_48 = "SSPM_SWPM_CORE__INFRA_STATE_RATIO\0dact,cact,idle,dcm"; | |
| node_47 = "SSPM_SWPM_CORE__VDEC_STATE_RATIO\0active,idle,off"; | |
| node_16 = "SSPM_CM_MGR_DSU_DVFS_OPP\0map_opp_50,map_opp_70,final,\0orig,L3_vote_opp,debounce_up,debounce_down"; | |
| node_25 = "SSPM_SWPM_CPU__CORE_NON_WFX_CTR\0cpu0,cpu1,cpu2,cpu3,cpu4,cpu5,cpu6,cpu7"; | |
| node_6 = "SSPM_CM_MGR_OPP\0v_dram_opp,v_dram_opp_cur,c_opp_cur_0,c_opp_cur_1,d_times_up,\0d_times_down"; | |
| node_8 = "SSPM_CM_MGR_BW\0total_bw"; | |
| node_0 = "SSPM_PTPOD\0_id,voltage"; | |
| node_50 = "SSPM_SWPM_CORE__DVFS\0vcore,ddr_freq"; | |
| node_19 = "SSPM_SWPM_CPU__CORE_IDLE_RATIO\0cpu0,cpu1,cpu2,cpu3,cpu4,cpu5,cpu6,cpu7"; | |
| node_56 = "SSPM_SWPM_ME__POWER\0disp,mdp,venc,vdec"; | |
| node_33 = "SSPM_SWPM_GPU__GPU_STATE_RATIO\0active,idle,off"; | |
| node_44 = "SSPM_SWPM_CORE__DISP_STATE_RATIO\0active,off"; | |
| node_20 = "SSPM_SWPM_CPU__CORE_OFF_RATIO\0cpu0,cpu1,cpu2,cpu3,cpu4,cpu5,cpu6,cpu7"; | |
| node_27 = "SSPM_SWPM_CPU__DSU_L3_BW\0L3_BW"; | |
| node_17 = "SSPM_CM_MGR_DSU_DVFS_THRESHOLD_FLAG\0up_L,up_B,up_BB,down_L,down_B,down_BB,\0up_L_flag,up_B_flag,up_BB_flag,\0down_L_flag,down_B_flag,down_BB_flag"; | |
| node_38 = "SSPM_SWPM_GPU__COUNTER\0GPU_ACTIVE,EXEC_INSTR_FMA,EXEC_INSTR_CVT,EXEC_INSTR_SFU,\0TEX,VARY_SLOT,L20,L21,L22,L23"; | |
| node_35 = "SSPM_SWPM_GPU__DVFS\0vgpu,gpu_freq"; | |
| node_10 = "SSPM_CM_MGR_VP_RATIO\0up0,up1,up2,up3,up4,up5,\0down0,down1,down2,down3,down4,down5"; | |
| node_62 = "SSPM_SLBC_REF\0venc,hifi3,sh_p2,sh_apu,mml,ainr,disp"; | |
| node_46 = "SSPM_SWPM_CORE__VENC_STATE_RATIO\0active,idle,off"; | |
| node_36 = "SSPM_SWPM_GPU__URATE\0alu_fma,alu_cvt,alu_sfu,tex,lsc,l2c,vary,tiler,rast"; | |
| node_5 = "SSPM_CM_MGR_POWER\0c_up_array_0,c_up_array_1,c_down_array_0,c_down_array_1,\0c_up_0,c_up_1,c_down_0,c_down_1,c_up,\0c_down,v_up,v_down,v2f_0,v2f_1"; | |
| node_64 = "SSPM_SLBC_PMU\0hit,miss"; | |
| node_66 = "SSPM_SWPM_CPU__DSU_PMU\0dsu_cycles"; | |
| node_22 = "SSPM_SWPM_CPU__CORE_PMU_L3DC\0cpu0,cpu1,cpu2,cpu3,cpu4,cpu5,cpu6,cpu7"; | |
| node_40 = "SSPM_SWPM_CORE__CAM_STATE_RATIO\0RAW_A_active,RAW_B_active,RAW_C_active,idle,off"; | |
| node_37 = "SSPM_SWPM_GPU__THERMAL\0thermal,lkg"; | |
| node_30 = "SSPM_SWPM_CPU__DVFS\0vproc2,vproc1,cpuL_freq,cpuB_freq,\0cpu_L_opp,cpu_B_opp,cci_volt,cci_freq,cci_opp"; | |
| node_9 = "SSPM_CM_MGR_CP_RATIO\0up0,up1,up2,up3,up4,up5,\0down0,down1,down2,down3,down4,down5"; | |
| node_63 = "SSPM_SLBC_BW\0mm,apu,mm_est"; | |
| node_15 = "SSPM_CM_MGR_DSU_DVFS_ACTIVE\0cpu0,cpu1,cpu2,cpu3,cpu4,cpu5,cpu6,cpu7"; | |
| node_39 = "SSPM_SWPM_GPU__POWER\0gpu"; | |
| node_53 = "SSPM_SWPM_DRAM__MEM_IDX\0read_bw,write_bw,\0srr_pct,ssr_pct,pdir_pct,\0phr_pct,acc_util,\0trans,mr4,ddr_freq"; | |
| node_14 = "SSPM_CM_MGR_DSU_DVFS_STALL\0cpu0,cpu1,cpu2,cpu3,cpu4,cpu5,cpu6,cpu7,l3_bw_val"; | |
| phandle = <0x1b2>; | |
| node_65 = "SSPM_SLBC_WAY\0venc,hifi3,sh_p2,sh_apu,mml,ainr,disp,slb,cpu,gpu,slc,left"; | |
| node_26 = "SSPM_SWPM_CPU__DSU_STATE_RATIO\0active,idle,dormant,off"; | |
| node_2 = "SSPM_QOS_BOUND_STATE\0ver,apu_num,idx,state,num,event,emibw_mon_total,\0emibw_mon_cpu,emibw_mon_gpu,emibw_mon_mm,\0emibw_mon_md,smibw_mon_gpu,smibw_mon_apu"; | |
| node_24 = "SSPM_SWPM_CPU__CORE_PMU_CYCLES\0cpu0,cpu1,cpu2,cpu3,cpu4,cpu5,cpu6,cpu7"; | |
| node_61 = "SSPM_SLBC_SLOT\0enable,force,done,buffer_used,f_buffer,cached_used,force_size"; | |
| node_45 = "SSPM_SWPM_CORE__ADSP_STATE_RATIO\0active,off"; | |
| node_7 = "SSPM_CM_MGR_RATIO\0ratio_0,ratio_1,ratio_2,ratio_3,ratio_4,\0ratio_5,ratio_6,ratio_7"; | |
| node_67 = "SSPM_SWPM_CPU__CORE_TEMP\0cpu0,cpu1,cpu2,cpu3,cpu4,cpu5,cpu6,cpu7"; | |
| node_60 = "__SSPM_GPU_APU_SSC_CNT__\0APU_0_R,APU_0_W,GPU_0_R,GPU_0_W,\0APU_1_R,APU_1_W,GPU_1_R,\0GPU_1_W"; | |
| node_43 = "SSPM_SWPM_CORE__MDP_STATE_RATIO\0active,off"; | |
| node_12 = "SSPM_CM_MGR_DSU_DVFS_PWR\0up_L,up_B,up_BB,up_DSU,cur_L,cur_B,cur_BB,cur_DSU,down_L,down_B,\0down_BB,down_DSU,total_up,total_cur,total_down"; | |
| node_32 = "SSPM_SWPM_CPU__POWER\0cpu_L,cpu_B,dsu,mcusys"; | |
| node_29 = "SSPM_SWPM_CPU__MCUSYS_EMI_BW\0cpu_emi_bw"; | |
| node_55 = "SSPM_SWPM_DRAM__POWER\0aphy_vddq_0p6v,aphy_vm_0p75v,aphy_vio_1p2v,dram_vddq_0p6v,\0dram_vdd2_1p25v,dram_vdd1_1p8v"; | |
| node_41 = "SSPM_SWPM_CORE__IMG_STATE_RATIO\0P2_active,P2_idle,MFB_active,WPE_active,off"; | |
| node_3 = "SSPM_CM_MGR_NON_WFX\0non_wfx_0,non_wfx_1,non_wfx_2,non_wfx_3,\0non_wfx_4,non_wfx_5,non_wfx_6,non_wfx_7"; | |
| node_69 = "SSPM_SWPM_CPU__PMU_TIMES\0idx_cnt,lock,idx_rechk,lock_rechk,valid,off_hint,diff_us"; | |
| }; | |
| mcupm-rts-header { | |
| node_1 = "__MCUPM_MET_L3CTL__\0op_policy,ct_portion,nct_portion,\t\t\tcpuqos_mode,dnth0,dnth1,upth0,upth1"; | |
| node_0 = "MCUPM_MET_UNIT_TEST\0test"; | |
| phandle = <0x1b1>; | |
| }; | |
| met_emi { | |
| ddrphy_ao_misc_cg_ctrl0 = <0x4ec>; | |
| dram_num = <0x02>; | |
| ddrphy_ao_misc_cg_ctrl2 = <0x4f4>; | |
| cen_emi_reg_size = <0x1000>; | |
| dram_type_default = <0x08>; | |
| dramc_ao_reg_size = <0x2000>; | |
| apmixedsys_reg_base = <0x1000c000>; | |
| chn_emi_reg_base = <0x10235000 0x10245000 0x10255000 0x10265000>; | |
| compatible = "mediatek,met_emi"; | |
| ddrphy_ao_reg_base = <0x10248000 0x10238000 0x10258000 0x10268000>; | |
| dramc_ver = <0x02>; | |
| met_emi_support_list = <0x05>; | |
| dram_freq_default = <0x1900>; | |
| slc_pmu_reg_size = <0x1000>; | |
| ddr_ratio_default = <0x08>; | |
| dramc_nao_reg_size = <0xb6c>; | |
| ddrphy_ao_reg_size = <0x1650>; | |
| phandle = <0x1b0>; | |
| emi_num = <0x01>; | |
| chn_emi_reg_size = <0xa90>; | |
| dramc_nao_reg_base = <0x10244000 0x10234000 0x10254000 0x10264000>; | |
| apmixedsys_reg_size = <0x410>; | |
| dramc_ao_reg_base = <0x10240000 0x10230000 0x10250000 0x10260000>; | |
| cen_emi_reg_base = <0x10219000 0x1021d000>; | |
| slc_pmu_reg_base = <0x10342000 0x10343000>; | |
| }; | |
| }; | |
| mmdvfs { | |
| clock-names = "disp0\0venc\0vdec\0mdp0\0cam\0img1\0ipe\0TOP_MAINPLL_D4\0TOP_UNIVPLL_D6\0TOP_UNIVPLL_D4_D2\0TOP_UNIVPLL_D6_D2\0TOP_TVDPLL\0TOP_MAINPLL_D5\0TOP_MMPLL_D4_D2\0TOP_MMPLL_D5_D2\0TOP_UNIVPLL_D4\0TOP_MMPLL_D6\0TOP_MMPLL_D7\0TOP_NPUPLL\0TOP_MAINPLL_D6\0TOP_UNIVPLL_D5_D2\0TOP_MAINPLL_D5_D2\0clk_mmpll_ck"; | |
| mediatek,mux_mdp0 = "TOP_MMPLL_D5_D2\0TOP_MMPLL_D4_D2\0TOP_MAINPLL_D5\0TOP_TVDPLL"; | |
| mediatek,action = <0x01>; | |
| operating-points-v2 = <0x47>; | |
| mediatek,hopping_clk_mmpll_ck = <0x887ea080 0xa3e9ab80 0xa3e9ab80 0xa3e9ab80>; | |
| compatible = "mediatek,mmdvfs"; | |
| mediatek,mux_venc = "TOP_UNIVPLL_D5_D2\0TOP_MAINPLL_D6\0TOP_MMPLL_D6\0TOP_UNIVPLL_D4"; | |
| mediatek,support_mux = "disp0\0venc\0vdec\0mdp0\0cam\0img1\0ipe"; | |
| mediatek,mux_img1 = "TOP_MMPLL_D5_D2\0TOP_MMPLL_D4_D2\0TOP_MMPLL_D6\0TOP_UNIVPLL_D4"; | |
| mediatek,support_hopping = "clk_mmpll_ck"; | |
| mediatek,mux_vdec = "TOP_MAINPLL_D5_D2\0TOP_UNIVPLL_D4_D2\0TOP_UNIVPLL_D6\0TOP_MAINPLL_D4"; | |
| dvfsrc-vcore-supply = <0x42>; | |
| clocks = <0x2a 0x04 0x2a 0x2b 0x2a 0x2c 0x2a 0x05 0x2a 0x08 0x2a 0x06 0x2a 0x07 0x2a 0x4b 0x2a 0x63 0x2a 0x5d 0x2a 0x64 0x2a 0x7d 0x2a 0x50 0x2a 0x76 0x2a 0x77 0x2a 0x5c 0x2a 0x78 0x2a 0x7a 0x2a 0x7c 0x2a 0x54 0x2a 0x61 0x2a 0x51 0x3b 0x07>; | |
| mediatek,mux_disp0 = "TOP_UNIVPLL_D6_D2\0TOP_UNIVPLL_D4_D2\0TOP_UNIVPLL_D6\0TOP_MAINPLL_D4"; | |
| mediatek,mux_ipe = "TOP_MMPLL_D5_D2\0TOP_UNIVPLL_D4_D2\0TOP_UNIVPLL_D6\0TOP_MAINPLL_D4"; | |
| mediatek,mux_cam = "TOP_NPUPLL\0TOP_MMPLL_D7\0TOP_MAINPLL_D4\0TOP_UNIVPLL_D4"; | |
| }; | |
| kte-drv { | |
| compatible = "kingtop,kte_drv"; | |
| status = "okay"; | |
| phandle = <0x1b3>; | |
| }; | |
| gps@18c00000 { | |
| pinctrl-6 = <0x1da>; | |
| pinctrl-5 = <0x1d9>; | |
| emi-region = <0x1d>; | |
| compatible = "mediatek,gps"; | |
| pinctrl-1 = <0x1d5>; | |
| pinctrl-names = "default\0gps_l1_lna_disable\0gps_l1_lna_dsp_ctrl\0gps_l1_lna_enable\0gps_l5_lna_disable\0gps_l5_lna_dsp_ctrl\0gps_l5_lna_enable"; | |
| status = "okay"; | |
| pinctrl-2 = <0x1d6>; | |
| emi-domain-ap = <0x00>; | |
| phandle = <0x1af>; | |
| pinctrl-4 = <0x1d8>; | |
| pinctrl-0 = <0x1d4>; | |
| emi-size = <0xfffff>; | |
| emi-offset = <0x400000>; | |
| pinctrl-3 = <0x1d7>; | |
| emi-domain-conn = <0x02>; | |
| }; | |
| camsv4_legacy@1a094000 { | |
| mediatek,larb = <0x44>; | |
| compatible = "mediatek,camsv4_legacy"; | |
| dma-ranges = <0x02 0x00 0x02 0x00 0x01 0x00>; | |
| reg = <0x00 0x1a094000 0x00 0x1000>; | |
| phandle = <0x102>; | |
| interrupts = <0x00 0x169 0x04 0x00>; | |
| }; | |
| md-cooler { | |
| compatible = "mediatek,mt6295-md-cooler"; | |
| phandle = <0xde>; | |
| pa1 { | |
| phandle = <0xdf>; | |
| mutt-pa1 { | |
| #cooling-cells = <0x02>; | |
| phandle = <0xe0>; | |
| }; | |
| }; | |
| }; | |
| cam1_inner_legacy@1a038000 { | |
| compatible = "mediatek,cam1_inner_legacy"; | |
| reg = <0x00 0x1a038000 0x00 0x8000>; | |
| }; | |
| memory-ssmr-features { | |
| wfd-region-based-size = <0x00 0x4000000>; | |
| wfd-page-based-size = <0x00 0x00>; | |
| compatible = "mediatek,memory-ssmr-features"; | |
| prot-region-based-size = <0x00 0x8000000>; | |
| tui-size = <0x00 0x4000000>; | |
| phandle = <0xdc>; | |
| svp-region-based-size = <0x00 0x18000000>; | |
| prot-page-based-size = <0x00 0x00>; | |
| svp-page-based-size = <0x00 0x00>; | |
| }; | |
| cam2_legacy@1a050000 { | |
| mediatek,larb = <0x46>; | |
| compatible = "mediatek,cam2_legacy"; | |
| dma-ranges = <0x02 0x00 0x02 0x00 0x01 0x00>; | |
| reg = <0x00 0x1a050000 0x00 0x8000>; | |
| phandle = <0xfc>; | |
| power-domains = <0x2d 0x0e>; | |
| interrupts = <0x00 0x161 0x04 0x00>; | |
| }; | |
| fpsgo { | |
| gcc_enable = <0x01>; | |
| compatible = "mediatek,fpsgo"; | |
| required-opps = <0x23>; | |
| interconnect-names = "fpsgo-perf-bw"; | |
| fbt_cpu_mask = <0xff 0xc0 0x3f 0xff>; | |
| phandle = <0xea>; | |
| interconnects = <0x22 0x01 0x22 0x00>; | |
| sbe_resceue_enable = <0x01>; | |
| }; | |
| syscon@1f000000 { | |
| compatible = "mediatek,mt6789-mdpsys\0syscon"; | |
| reg = <0x00 0x1f000000 0x00 0x1000>; | |
| phandle = <0x2c>; | |
| #clock-cells = <0x01>; | |
| }; | |
| mt6366_temp { | |
| io-channel-names = "pmic6366_ts1\0pmic6366_ts2\0pmic6366_ts3\0pmic6366_ts4"; | |
| compatible = "mediatek,mt6366-pmic-temp"; | |
| #thermal-sensor-cells = <0x01>; | |
| nvmem-cell-names = "mt6366_e_data"; | |
| nvmem-cells = <0x1a>; | |
| io-channels = <0x19 0x05 0x19 0x06 0x19 0x07 0x19 0x08>; | |
| phandle = <0x20>; | |
| }; | |
| firmware { | |
| phandle = <0xd6>; | |
| scmi { | |
| mbox-names = "tx\0rx"; | |
| #size-cells = <0x00>; | |
| compatible = "arm,scmi"; | |
| mboxes = <0x14 0x00 0x14 0x01>; | |
| shmem = <0x15 0x16>; | |
| #address-cells = <0x01>; | |
| phandle = <0xd7>; | |
| protocol@80 { | |
| scmi_smi = <0x06>; | |
| scmi_pmic = <0x02>; | |
| scmi_plt = <0x05>; | |
| scmi_apmcupm = <0x08>; | |
| scmi_cm = <0x07>; | |
| reg = <0x80>; | |
| phandle = <0xd8>; | |
| scmi_qos = <0x01>; | |
| scmi_gpupm = <0x04>; | |
| scmi_met = <0x03>; | |
| }; | |
| }; | |
| android { | |
| serialno = "KT00922023054296195"; | |
| vbmeta.size = "10368"; | |
| mode = "normal"; | |
| compatible = "android,firmware"; | |
| vbmeta.digest = "983fd2dc4b6c6994cef02cb2b3e094e44d21fd7efc8d4168dba0019deca40832"; | |
| hardware = "mt6789"; | |
| vbmeta.hash_alg = "sha256"; | |
| phandle = <0xd9>; | |
| }; | |
| }; | |
| cam3_inner_legacy@1a078000 { | |
| compatible = "mediatek,cam3_inner_legacy"; | |
| reg = <0x00 0x1a078000 0x00 0x8000>; | |
| }; | |
| mmdvfs-debug { | |
| compatible = "mediatek,mmdvfs-debug"; | |
| force-step0 = <0x01>; | |
| dvfsrc-vcore-supply = <0x42>; | |
| release-step0 = <0x01>; | |
| }; | |
| charger-cooler { | |
| compatible = "mediatek,mt6375-charger-cooler"; | |
| #cooling-cells = <0x02>; | |
| phandle = <0xe1>; | |
| }; | |
| lastbus { | |
| enabled = <0x01>; | |
| sw_version = <0x01>; | |
| compatible = "mediatek,lastbus"; | |
| timeout_type = <0x00>; | |
| timeout_ms = <0xc8>; | |
| phandle = <0xd5>; | |
| monitors { | |
| monitor2 { | |
| base = <0x10042000>; | |
| bus_freq_mhz = <0x4e>; | |
| num_ports = <0x0e>; | |
| monitor_name = "debug_ctrl_ao_FMEM_AO"; | |
| }; | |
| monitor4 { | |
| base = <0x10040000>; | |
| bus_freq_mhz = <0x4e>; | |
| num_ports = <0x06>; | |
| monitor_name = "debug_ctrl_ao_PERI_PAR_AO"; | |
| }; | |
| monitor1 { | |
| base = <0x1002b000>; | |
| bus_freq_mhz = <0x4e>; | |
| num_ports = <0x22>; | |
| monitor_name = "debug_ctrl_ao_PERI_AO"; | |
| }; | |
| monitor3 { | |
| base = <0x1002e000>; | |
| bus_freq_mhz = <0x4e>; | |
| num_ports = <0x13>; | |
| monitor_name = "debug_ctrl_ao_PERI_AO2"; | |
| }; | |
| monitor5 { | |
| base = <0x10023000>; | |
| bus_freq_mhz = <0x4e>; | |
| num_ports = <0x16>; | |
| monitor_name = "debug_ctrl_ao_INFRA_AO"; | |
| }; | |
| }; | |
| }; | |
| __symbols__ { | |
| scmi = "/firmware/scmi"; | |
| dram_s0 = "/mtk_lpm/resource-ctrl-list/dram_s0"; | |
| mmc1_pins_uhs = "/soc/pinctrl/mmc1@0"; | |
| vcp = "/soc/vcp@1ec00000"; | |
| disp_ovl0 = "/soc/disp_ovl0@14005000"; | |
| mt6358_vsim2_reg = "/soc/pwrap@10026000/mt6366/mt6358regulator/ldo_vsim2"; | |
| usb_role = "/soc/extcon_usb/port/endpoint@0"; | |
| btif = "/soc/btif@1100c000"; | |
| disp_mutex0 = "/soc/disp_mutex@14001000"; | |
| mt6358_vcamd_reg = "/soc/pwrap@10026000/mt6366/mt6358regulator/ldo_vcamd"; | |
| i2c6 = "/soc/i2c@1101a000"; | |
| pbm = "/pbm"; | |
| mt6358_vcn33_wifi_reg = "/soc/pwrap@10026000/mt6366/mt6358regulator/ldo_vcn33_wifi"; | |
| gce = "/soc/gce@10228000"; | |
| systimer = "/soc/systimer@10017000"; | |
| aud_clk_miso_off = "/soc/pinctrl/aud_clk_miso_off"; | |
| cm_mgr = "/cm_mgr@0c530000"; | |
| syspll = "/mtk_lpm/resource-ctrl-list/syspll"; | |
| ssmr_cma_mem = "/reserved-memory/ssmr-reserved-cma_memory"; | |
| drm_wv = "/soc/drm_wv"; | |
| mt6358_vmodem_reg = "/soc/pwrap@10026000/mt6366/mt6358regulator/buck_vmodem"; | |
| mt6358_vmch_eint_low = "/soc/pwrap@10026000/mt6366/mt6358regulator/VMCH_EINT_LOW"; | |
| rt5133_ldo4 = "/soc/i2c@11017000/rt5133@18/regulators/LDO4"; | |
| spi5 = "/soc/spi5@11019000"; | |
| cpu3 = "/cpus/cpu@003"; | |
| pmic_efuse = "/soc/pwrap@10026000/mt6366/mt6358-efuse"; | |
| soc_max_crit = "/thermal-zones/soc_max/trips/soc_max_crit@0"; | |
| mdp_rdma0 = "/soc/mdp_rdma0@1f003000"; | |
| mmc1_pins_pull_down = "/soc/pinctrl/mmc1@1"; | |
| rt5133_ldo1 = "/soc/i2c@11017000/rt5133@18/regulators/LDO1"; | |
| opp_table_cam = "/opp-table-cam"; | |
| disp_wdma0 = "/soc/disp_wdma0@14014000"; | |
| disp_gamma0 = "/soc/disp_gamma0@1400d000"; | |
| clusteroff_l = "/cpus/idle-states/clusteroff_l"; | |
| mt6358_va09_reg = "/soc/pwrap@10026000/mt6366/mt6358regulator/ldo_va09"; | |
| dvfsrc_freq_opp1 = "/soc/dvfsrc@10012000/opp1"; | |
| i2c4 = "/soc/i2c@11eb1000"; | |
| timer = "/timer"; | |
| mdpm = "/mdpm"; | |
| goodix_fp = "/soc/fingerprint"; | |
| disp_dither0 = "/soc/disp_dither0@1400f000"; | |
| disable_unused = "/disable_unused"; | |
| kte_drv = "/kte-drv"; | |
| mrdump_ext_rst = "/mrdump_ext_rst"; | |
| mtk_composite_v4l2_1 = "/mtk_composite_v4l2_1"; | |
| auxadc = "/soc/auxadc@11001000"; | |
| level_usb = "/mtk_lpm/irq-remain-list/level_usb"; | |
| smi_larb4 = "/soc/smi_larb4@1602e000"; | |
| camsv5_legacy = "/camsv5_legacy@1a095000"; | |
| ext_32k = "/soc/pwrap@10026000/mt6366/mt6358rtc/ext_32k"; | |
| rt5133_ldo2 = "/soc/i2c@11017000/rt5133@18/regulators/LDO2"; | |
| mt6358_vcn28_reg = "/soc/pwrap@10026000/mt6366/mt6358regulator/ldo_vcn28"; | |
| mt6358_vcamio_reg = "/soc/pwrap@10026000/mt6366/mt6358regulator/ldo_vcamio"; | |
| infracfg_ao_clk = "/syscon@10001000"; | |
| mt6358_vsim1_reg = "/soc/pwrap@10026000/mt6366/mt6358regulator/ldo_vsim1"; | |
| disp_ccorr0 = "/soc/disp_ccorr0@1400b000"; | |
| mt6358_vdram2_reg = "/soc/pwrap@10026000/mt6366/mt6358regulator/ldo_vdram2"; | |
| ccifdriver = "/soc/ccifdriver@10209000"; | |
| cpu_pll = "/soc/mcusys_pll1u_top@1000c000"; | |
| fg_init = "/soc/pwrap@10026000/mt6366/mt6358rtc/fg_init"; | |
| s2idle = "/cpus/idle-states/s2idle"; | |
| dfd_mcu = "/soc/dfd_mcu@0c530000"; | |
| pwrap = "/soc/pwrap@10026000"; | |
| cpuhvfs = "/cpuhvfs@00114400"; | |
| mt6358_vs1_reg = "/soc/pwrap@10026000/mt6366/mt6358regulator/buck_vs1"; | |
| system_mem = "/cpus/idle-states/system_mem"; | |
| gate_ic = "/soc/i2c@1101a000/gate_ic@11"; | |
| camsv7_legacy = "/camsv7_legacy@1a097000"; | |
| md_cooler = "/md-cooler"; | |
| mtk_ssc = "/mtk_ssc"; | |
| mcusys_ctrl = "/mtk_lpm/mcusys-ctrl@0c53a000"; | |
| ipesys_clk = "/syscon@1b000000"; | |
| aud_dat_miso1_off = "/soc/pinctrl/aud_dat_miso1_off"; | |
| camsv2_legacy = "/camsv2_legacy@1a092000"; | |
| bp_thl = "/bp_thl"; | |
| gpufreq = "/soc/gpufreq"; | |
| btcvsd_snd = "/soc/mtk-btcvsd-snd@18050000"; | |
| mdp_wrot0 = "/soc/mdp_wrot0@1f00a000"; | |
| mt6358_vcn18_reg = "/soc/pwrap@10026000/mt6366/mt6358regulator/ldo_vcn18"; | |
| mobicore = "/soc/mobicore"; | |
| smi_larb14 = "/soc/smi_larb14@1a002000"; | |
| mt6358_vsram_core_reg = "/soc/pwrap@10026000/mt6366/mt6358regulator/ldo_vsram_core"; | |
| mt6366keys = "/soc/pwrap@10026000/mt6366/mt6366keys"; | |
| accdet = "/soc/pwrap@10026000/mt6366/accdet"; | |
| subpmic_pmu_eint = "/subpmic_pmu_eint"; | |
| cpu0 = "/cpus/cpu@000"; | |
| apccci_mdo1 = "/soc/md_power_o1"; | |
| mtkfb = "/soc/mtkfb@0"; | |
| mtk_leds = "/soc/mtk_leds"; | |
| touch = "/touch"; | |
| mt6358_dynamic_loading_throttling = "/soc/pwrap@10026000/mt6366/mtk_dynamic_loading_throttling"; | |
| venc_gcon_clk = "/syscon@17000000"; | |
| u2phy0 = "/soc/usb-phy@11f40000"; | |
| cam_smi_4x1_sub_common0 = "/soc/cam_smi_4x1_sub_comm0@1a00d000"; | |
| spi4 = "/soc/spi4@11018000"; | |
| img0_smi_2x1_sub_common = "/soc/img0_smi_2x1_sub_comm@1502f000"; | |
| performance = "/soc/performance-controller@0011bc00"; | |
| disp_color0 = "/soc/disp_color0@14009000"; | |
| gic = "/interrupt-controller"; | |
| aud_gpio_i2s3_on = "/soc/pinctrl/aud_gpio_i2s3_on"; | |
| aud_clk_mosi_on = "/soc/pinctrl/aud_clk_mosi_on"; | |
| apdma = "/soc/dma-controller@10217800"; | |
| scp_audio_mbox = "/soc/scp_audio_mbox@107ff000"; | |
| mtk_ctd = "/mtk_ctd"; | |
| mt6358_vsram_gpu_reg = "/soc/pwrap@10026000/mt6366/mt6358regulator/ldo_vsram_gpu"; | |
| seninf_top = "/soc/seninf_top@1a004000"; | |
| level_btif_tx = "/mtk_lpm/irq-remain-list/level_btif_tx"; | |
| smi_larb7 = "/soc/smi_larb7@17010000"; | |
| mt6358_vproc11_reg = "/soc/pwrap@10026000/mt6366/mt6358regulator/buck_vproc11"; | |
| i2c8 = "/soc/i2c@11eb2000"; | |
| lpm_sysram = "/mtk_lpm/lpm_sysram@0011b500"; | |
| mt6358_batoc_throttle = "/soc/pwrap@10026000/mt6366/mtk_battery_oc_throttling"; | |
| dvfsrc_freq_opp3 = "/soc/dvfsrc@10012000/opp3"; | |
| smi_pd_cam_rawa = "/soc/smi_pd_cam_rawa"; | |
| smi_larb1 = "/soc/smi_larb1@14004000"; | |
| camisp_legacy = "/camisp_legacy@1a000000"; | |
| clk13m = "/clocks/clk13m"; | |
| tboard_thermistor2 = "/thermal-ntc2"; | |
| mt6358_vldo28_reg = "/soc/pwrap@10026000/mt6366/mt6358regulator/ldo_vldo28"; | |
| mt6358_vcn33_bt_reg = "/soc/pwrap@10026000/mt6366/mt6358regulator/ldo_vcn33_bt"; | |
| mali = "/soc/mali@13000000"; | |
| camsys_rawa_clk = "/syscon@1a04f000"; | |
| smi_larb20 = "/soc/smi_larb20@1b00f000"; | |
| camera_af_hw_node = "/camera_af_hw_node"; | |
| cpu7 = "/cpus/cpu@101"; | |
| snd_scp_audio = "/soc/snd_scp_audio"; | |
| dfd_cache = "/soc/dfd_mcu@0c530000/dfd_cache"; | |
| aud_dat_mosi_on = "/soc/pinctrl/aud_dat_mosi_on"; | |
| gpu_mali_opp = "/soc/opp-table0"; | |
| ccci_scp = "/soc/ccci_scp"; | |
| i2c2 = "/soc/i2c@11eb0000"; | |
| mt6375_adc = "/soc/i2c@11017000/mt6375@34/adc"; | |
| u2_phy_data = "/soc/efuse@11c10000/u2_phy_data"; | |
| mddriver = "/soc/mddriver"; | |
| mutt_pa1 = "/md-cooler/pa1/mutt-pa1"; | |
| mdp_rsz0 = "/soc/mdp_rsz0@1f008000"; | |
| pmic_auxadc = "/soc/pwrap@10026000/mt6366/mt635x-auxadc"; | |
| aud_gpio_i2s0_on = "/soc/pinctrl/aud_gpio_i2s0_on"; | |
| camsys_rawc_legacy = "/camsys_rawc_legacy@1a08f000"; | |
| mt6358codec = "/soc/pwrap@10026000/mt6366/mt6358codec"; | |
| dpmaif = "/soc/dpmaif@10014000"; | |
| imp_iic_wrap_w_clk = "/syscon@11E02000"; | |
| disp_mtee_sec = "/soc/disp_mtee_sec"; | |
| spi2 = "/soc/spi2@11012000"; | |
| vdec_fmt = "/soc/vdec_fmt@16080000"; | |
| cpu2 = "/cpus/cpu@002"; | |
| disp_iommu_bank2 = "/soc/iommu@14018000"; | |
| spmtwam = "/spmtwam@10006000"; | |
| mmc0_pins_default = "/soc/pinctrl/mmc0default"; | |
| mcupm_rts_header = "/met/mcupm-rts-header"; | |
| vow_dat_miso_on = "/soc/pinctrl/vow_dat_miso_on"; | |
| aud_clk_miso_on = "/soc/pinctrl/aud_clk_miso_on"; | |
| efuse = "/soc/efuse@11c10000"; | |
| mt6358_vemc_reg = "/soc/pwrap@10026000/mt6366/mt6358regulator/ldo_vemc"; | |
| mt6358_vsram_proc11_reg = "/soc/pwrap@10026000/mt6366/mt6358regulator/ldo_vsram_proc11"; | |
| pe = "/pe"; | |
| mt6375 = "/soc/i2c@11017000/mt6375@34"; | |
| u2port0 = "/soc/usb-phy@11f40000/usb-phy@11f40000"; | |
| flashlight_core = "/flashlight_core"; | |
| reserved_memory = "/reserved-memory"; | |
| mcupm = "/mcupm@0c540000"; | |
| mt6358regulator = "/soc/pwrap@10026000/mt6366/mt6358regulator"; | |
| usb_meta = "/soc/usb_meta"; | |
| opp_table_disp0 = "/opp-table-disp0"; | |
| scmi_tinysys = "/firmware/scmi/protocol@80"; | |
| mt6358_vrf18_reg = "/soc/pwrap@10026000/mt6366/mt6358regulator/ldo_vrf18"; | |
| aud_dat_miso0_off = "/soc/pinctrl/aud_dat_miso0_off"; | |
| spm_cond_cg = "/mtk_lpm/spm-cond-list/spm_cond_cg"; | |
| gps = "/gps@18c00000"; | |
| clkitg = "/clkitg"; | |
| dvfsrc = "/soc/dvfsrc@10012000"; | |
| rt5133_ldo5 = "/soc/i2c@11017000/rt5133@18/regulators/LDO5"; | |
| dispsys_config_clk = "/syscon@14000000"; | |
| mtk_lpm = "/mtk_lpm"; | |
| scp_gpio = "/soc/scp_gpio@10005000"; | |
| i2c1 = "/soc/i2c@11e01000"; | |
| dvfsrc_vscp = "/soc/dvfsrc@10012000/dvfsrc-vscp"; | |
| disp_rsz0 = "/soc/disp_rsz0@14008000"; | |
| mt6358_vcama1_reg = "/soc/pwrap@10026000/mt6366/mt6358regulator/ldo_vcama1"; | |
| md1_sim1_hot_plug_eint = "/soc/MD1_SIM1_HOT_PLUG_EINT"; | |
| watchdog = "/soc/watchdog@10007000"; | |
| vow_clk_miso_off = "/soc/pinctrl/vow_clk_miso_off"; | |
| clusteroff_b = "/cpus/idle-states/clusteroff_b"; | |
| thermal_zones = "/thermal-zones"; | |
| pe4 = "/pe4"; | |
| imp_iic_wrap_n_clk = "/syscon@11F01000"; | |
| mt6358_lbat = "/soc/pwrap@10026000/mt6366/pmic_lbat_service"; | |
| mmc1_pins_default = "/soc/pinctrl/mmc1default"; | |
| infracfg_rst = "/syscon@10001000/reset-controller"; | |
| u3fpgaphy = "/soc/usb-phy"; | |
| aud_dat_mosi_off = "/soc/pinctrl/aud_dat_mosi_off"; | |
| fhctl = "/fhctl@1000ce00"; | |
| mt6358_vbif28_reg = "/soc/pwrap@10026000/mt6366/mt6358regulator/ldo_vbif28"; | |
| spm_cond_pll = "/mtk_lpm/spm-cond-list/spm_cond_pll"; | |
| opp_table_venc = "/opp-table-venc"; | |
| smi_larb13 = "/soc/smi_larb13@1a001000"; | |
| consys = "/soc/consys@18002000"; | |
| memory_ssmr_features = "/memory-ssmr-features"; | |
| emichn = "/soc/emichn@10245000"; | |
| pd_adapter = "/pd_adapter"; | |
| mt6358_vsram_proc12_reg = "/soc/pwrap@10026000/mt6366/mt6358regulator/ldo_vsram_proc12"; | |
| rt5133_ldo3 = "/soc/i2c@11017000/rt5133@18/regulators/LDO3"; | |
| spi0 = "/soc/spi0@1100a000"; | |
| pa1 = "/md-cooler/pa1"; | |
| usb_boost = "/soc/usb_boost_manager"; | |
| rt5133 = "/soc/i2c@11017000/rt5133@18"; | |
| mt6358_vcama2_reg = "/soc/pwrap@10026000/mt6366/mt6358regulator/ldo_vcama2"; | |
| dram_s1 = "/mtk_lpm/resource-ctrl-list/dram_s1"; | |
| emimpu = "/soc/emimpu@10226000"; | |
| drm = "/soc/drm@1000d000"; | |
| disp_rdma0 = "/soc/disp_rdma0@14007000"; | |
| mt6358_vaux18_reg = "/soc/pwrap@10026000/mt6366/mt6358regulator/ldo_vaux18"; | |
| dcm = "/dcm@10001000"; | |
| cpu_power_throttling = "/cpu_power_throttling"; | |
| disp_dsc_wrap0 = "/soc/disp_dsc_wrap0@14012000"; | |
| smi_pd_cam_rawb = "/soc/smi_pd_cam_rawb"; | |
| aud_dat_miso1_on = "/soc/pinctrl/aud_dat_miso1_on"; | |
| pe5 = "/pe5"; | |
| i2c7 = "/soc/i2c@11f00000"; | |
| mt6358rtc = "/soc/pwrap@10026000/mt6366/mt6358rtc"; | |
| u3fpgaport0 = "/soc/usb-phy/usb-phy@0"; | |
| mmc0 = "/soc/mmc@11230000"; | |
| tboard_thermistor1 = "/thermal-ntc1"; | |
| ipe_smi_2x1_sub_common = "/soc/ipe_smi_2x1_sub_comm@1b00e000"; | |
| sspm = "/sspm@10400000"; | |
| mt6358_vmch_eint_high = "/soc/pwrap@10026000/mt6366/mt6358regulator/VMCH_EINT_HIGH"; | |
| scp_infra = "/soc/scp_infra@10001000"; | |
| img1_smi_2x1_sub_common = "/soc/img1_smi_2x1_sub_comm@1401e000"; | |
| kd_camera_hw1 = "/soc/kd_camera_hw1@1a004000"; | |
| rt5133_gpio2 = "/soc/odm/rt5133-gpio2"; | |
| chosen = "/chosen"; | |
| dvfsrc_freq_opp6 = "/soc/dvfsrc@10012000/opp6"; | |
| extcon_usb = "/soc/extcon_usb"; | |
| android = "/firmware/android"; | |
| mcusysoff = "/cpus/idle-states/mcusysoff"; | |
| pio = "/soc/pinctrl"; | |
| aud_clk_mosi_off = "/soc/pinctrl/aud_clk_mosi_off"; | |
| mdp_tdshp0 = "/soc/mdp_tdshp0@1f00c000"; | |
| masp = "/soc/masp@1000a000"; | |
| mtee_svp = "/soc/mtee_svp"; | |
| edge_keypad = "/mtk_lpm/irq-remain-list/edge_keypad"; | |
| smi_disp_common = "/soc/smi_disp_comm@14002000"; | |
| vow_dat_miso_off = "/soc/pinctrl/vow_dat_miso_off"; | |
| camsys_main_clk = "/syscon@1a000000"; | |
| mmqos = "/soc/interconnect"; | |
| dvfsrc_vcore = "/soc/dvfsrc@10012000/dvfsrc-vcore"; | |
| charger_cooler = "/charger-cooler"; | |
| gpio_usage_mapping = "/soc/gpio_usage_mapping"; | |
| disp_pwm = "/soc/disp_pwm0@1100e000"; | |
| i2c0 = "/soc/i2c@11e00000"; | |
| rc_bus26m = "/mtk_lpm/constraint-list/rc_bus26m"; | |
| spi1 = "/soc/spi1@11010000"; | |
| scpsys = "/power-controller@10006000"; | |
| mdp_mutex = "/soc/mdp_mutex@1f001000"; | |
| i2c9 = "/soc/i2c@11eb3000"; | |
| clk_ao = "/clk_ao"; | |
| camsys_rawb_clk = "/syscon@1a06f000"; | |
| disp_iommu_bank4 = "/soc/iommu@1401a000"; | |
| utos = "/utos"; | |
| mt6358_vmc_reg = "/soc/pwrap@10026000/mt6366/mt6358regulator/ldo_vmc"; | |
| touch_panel = "/touch_panel"; | |
| uart0 = "/soc/serial@11002000"; | |
| mt6366_thermal_efuse = "/soc/pwrap@10026000/mt6366/mt6358-efuse/mt6366_e_data"; | |
| scmi_rx_shmem = "/ssram2@10460000/tiny_mbox@1"; | |
| lk_charger = "/lk_charger"; | |
| ulposc = "/clocks/ulposc"; | |
| imp_iic_wrap_en_clk = "/syscon@11EB4000"; | |
| smi_larb16 = "/soc/smi_larb16@1a00f000"; | |
| mt6358_vefuse_reg = "/soc/pwrap@10026000/mt6366/mt6358regulator/ldo_vefuse"; | |
| rt5133_ldo7 = "/soc/i2c@11017000/rt5133@18/regulators/LDO7"; | |
| mt6358_vfe28_reg = "/soc/pwrap@10026000/mt6366/mt6358regulator/ldo_vfe28"; | |
| dsi_te = "/soc/dsi_te"; | |
| i2c5 = "/soc/i2c@11017000"; | |
| mt6358_vaud28_reg = "/soc/pwrap@10026000/mt6366/mt6358regulator/ldo_vaud28"; | |
| disp_iommu_bank1 = "/soc/iommu@14017000"; | |
| dramc = "/soc/dramc@10230000"; | |
| rt5133_ldo6 = "/soc/i2c@11017000/rt5133@18/regulators/LDO6"; | |
| disp_smi_2x1_sub_common_u1 = "/soc/disp_smi_2x1_sub_comm1@1401c000"; | |
| pwraph = "/soc/pwraphal@10026000"; | |
| cam2_legacy = "/cam2_legacy@1a050000"; | |
| disp_iommu = "/soc/iommu@14016000"; | |
| smi_pd_cam_main = "/soc/smi_pd_cam_main"; | |
| disp_smi_2x1_sub_common_u0 = "/soc/disp_smi_2x1_sub_comm0@1401b000"; | |
| gpufreq_wrapper = "/soc/gpufreq_wrapper"; | |
| mt6358_vproc12_reg = "/soc/pwrap@10026000/mt6366/mt6358regulator/buck_vproc12"; | |
| mtk_gauge = "/soc/pwrap@10026000/mt6366/mtk_gauge"; | |
| disp_aal0 = "/soc/disp_aal0@1400c000"; | |
| scp_clk_ctrl = "/soc/scp_clk_ctrl@10721000"; | |
| smi_larb2 = "/soc/smi_larb2@1f002000"; | |
| qos = "/qos@0011bb00"; | |
| aud_gpio_i2s0_off = "/soc/pinctrl/aud_gpio_i2s0_off"; | |
| mmc1 = "/soc/mmc@11240000"; | |
| efuse_segment = "/soc/efuse@11c10000/segment@78"; | |
| swpm = "/swpm"; | |
| ged = "/soc/ged"; | |
| level_btif_rx = "/mtk_lpm/irq-remain-list/level_btif_rx"; | |
| disp_ovl0_2l = "/soc/disp_ovl0_2l@14006000"; | |
| md_auxadc = "/soc/md_auxadc"; | |
| md_power_throttling = "/md_power_throttling"; | |
| clk32k = "/clocks/clk32k"; | |
| mt6358_va12_reg = "/soc/pwrap@10026000/mt6366/mt6358regulator/ldo_va12"; | |
| mdp_hdr0 = "/soc/mdp_hdr0@1f007000"; | |
| mt6358_vibr_reg = "/soc/pwrap@10026000/mt6366/mt6358regulator/ldo_vibr"; | |
| aud_gpio_i2s3_off = "/soc/pinctrl/aud_gpio_i2s3_off"; | |
| wifi = "/soc/wifi@18000000"; | |
| sound = "/soc/sound"; | |
| hwrng = "/hwrng"; | |
| scmi_tx_shmem = "/ssram1@10450000/tiny_mbox@0"; | |
| mt6358_vusb_reg = "/soc/pwrap@10026000/mt6366/mt6358regulator/ldo_vusb"; | |
| mfg_top_config_clk = "/syscon@13fbf000"; | |
| vow_clk_miso_on = "/soc/pinctrl/vow_clk_miso_on"; | |
| topckgen_clk = "/syscon@10000000"; | |
| tinysys_mbox = "/tinysys_mbox@10451000"; | |
| fg_soc = "/soc/pwrap@10026000/mt6366/mt6358rtc/fg_soc"; | |
| mt6358_vsram_others_reg = "/soc/pwrap@10026000/mt6366/mt6358regulator/ldo_vsram_others"; | |
| vcu = "/soc/vcu@16000000"; | |
| backlight_cooler = "/backlight-cooler"; | |
| infracfg_ao = "/soc/infracfg_ao@10001000"; | |
| cam_smi_3x1_sub_common1 = "/soc/cam_smi_3x1_sub_comm1@1a00c000"; | |
| rt5133_ldo8 = "/soc/i2c@11017000/rt5133@18/regulators/LDO8"; | |
| mt6358_vsram_others_sshub_reg = "/soc/pwrap@10026000/mt6366/mt6358regulator/ldo_vsram_others_sshub"; | |
| cpu_mcucfg = "/soc/mcusys_ao_cfg@0c530000"; | |
| afe = "/soc/mt6789-afe-pcm@11210000"; | |
| camsv3_legacy = "/camsv3_legacy@1a093000"; | |
| cpuoff_b = "/cpus/idle-states/cpuoff_b"; | |
| clk26m = "/clocks/clk26m"; | |
| uart1 = "/soc/serial@11003000"; | |
| sspm_rts_header = "/met/sspm-rts-header"; | |
| irtx_pwm = "/soc/irtx_pwm"; | |
| afe_clk = "/syscon@11210000"; | |
| cpupm_sysram = "/mtk_lpm/cpupm-sysram@0011b000"; | |
| cam3_legacy = "/cam3_legacy@1a070000"; | |
| smi_larb9 = "/soc/smi_larb9@1502e000"; | |
| dvfsrc_freq_opp5 = "/soc/dvfsrc@10012000/opp5"; | |
| eas_info = "/soc/eas_info"; | |
| gpio = "/soc/gpio@10005000"; | |
| imp_iic_wrap_c_clk = "/syscon@1101B000"; | |
| mdp = "/soc/mdp@1f000000"; | |
| camsv4_legacy = "/camsv4_legacy@1a094000"; | |
| mt6358_vcore_reg = "/soc/pwrap@10026000/mt6366/mt6358regulator/buck_vcore"; | |
| mt6375_typec = "/soc/i2c@11017000/mt6375@34/tcpc"; | |
| seninf_n3d_top = "/soc/seninf_n3d_top@1a004000"; | |
| disp_iommu_bank3 = "/soc/iommu@14019000"; | |
| i2c3 = "/soc/i2c@11015000"; | |
| ufshci = "/soc/ufshci@11270000"; | |
| usb = "/soc/usb0@11200000"; | |
| aud_dat_miso0_on = "/soc/pinctrl/aud_dat_miso0_on"; | |
| imgsys1_clk = "/syscon@15020000"; | |
| lvts = "/soc/lvts@1100B000"; | |
| mt6375_otg_vbus = "/soc/i2c@11017000/mt6375@34/chg/otg"; | |
| mdp_rsz1 = "/soc/mdp_rsz1@1f009000"; | |
| rc_syspll = "/mtk_lpm/constraint-list/rc_syspll"; | |
| mt6358_vio28_reg = "/soc/pwrap@10026000/mt6366/mt6358regulator/ldo_vio28"; | |
| bus26m = "/mtk_lpm/resource-ctrl-list/bus26m"; | |
| musb_drd_switch = "/soc/usb0@11200000/port/endpoint@0"; | |
| dispsys_config = "/soc/dispsys_config@14000000"; | |
| pericfg = "/soc/pericfg@10003000"; | |
| pmic = "/soc/pwrap@10026000/mt6366"; | |
| clock_buffer_ctrl = "/soc/clock_buffer_ctrl"; | |
| mdp_aal0 = "/soc/mdp_aal0@1f005000"; | |
| met_emi = "/met/met_emi"; | |
| cam1_legacy = "/cam1_legacy@1a030000"; | |
| opp_table_mdp0 = "/opp-table-mdp0"; | |
| cpu1 = "/cpus/cpu@001"; | |
| imgsys_config = "/soc/imgsys_config@15020000"; | |
| lvts_e_data1 = "/soc/efuse@11c10000/data1"; | |
| smi_larb0 = "/soc/smi_larb0@14003000"; | |
| rc_cpu_buck_ldo = "/mtk_lpm/constraint-list/rc_cpu_buck_ldo"; | |
| rt5133_gpio1 = "/soc/odm/rt5133-gpio1"; | |
| infra = "/mtk_lpm/resource-ctrl-list/infra"; | |
| mt6358_vmch_reg = "/soc/pwrap@10026000/mt6366/mt6358regulator/ldo_vmch"; | |
| opp_table_img = "/opp-table-img"; | |
| fpsgo = "/fpsgo"; | |
| lvts_e_data2 = "/soc/efuse@11c10000/data2"; | |
| ltepa_ntc = "/thermal-zones/ltepa_ntc"; | |
| mt6366_temp = "/mt6366_temp"; | |
| camsys_rawa_legacy = "/camsys_rawa_legacy@1a04f000"; | |
| firmware = "/firmware"; | |
| md1_sim2_hot_plug_eint = "/soc/MD1_SIM2_HOT_PLUG_EINT"; | |
| system_bus = "/cpus/idle-states/system_bus"; | |
| edge_mdwdt = "/mtk_lpm/irq-remain-list/edge_mdwdt"; | |
| lastbus = "/lastbus"; | |
| gce_sec = "/soc/gce_mbox_sec@10228000"; | |
| mdp_wrot1 = "/soc/mdp_wrot1@1f00b000"; | |
| mt6358_vgpu_reg = "/soc/pwrap@10026000/mt6366/mt6358regulator/buck_vgpu"; | |
| mt6358_vdram1_reg = "/soc/pwrap@10026000/mt6366/mt6358regulator/buck_vdram1"; | |
| opp_table_ipe = "/opp-table-ipe"; | |
| rc_dram = "/mtk_lpm/constraint-list/rc_dram"; | |
| snd_scp_ultra = "/soc/snd_scp_ultra"; | |
| mt6366_clock_buffer = "/soc/pwrap@10026000/mt6366/mt6366_clock_buffer"; | |
| cpu6 = "/cpus/cpu@100"; | |
| spi3 = "/soc/spi3@11013000"; | |
| mdpsys_config = "/soc/mdpsys_config@1f000000"; | |
| smi_larb17 = "/soc/smi_larb17@1a010000"; | |
| mt6358_vs2_reg = "/soc/pwrap@10026000/mt6366/mt6358regulator/buck_vs2"; | |
| regulator_vibrator = "/soc/regulator_vibrator"; | |
| dsi0 = "/soc/dsi@14013000"; | |
| therm_intf = "/therm_intf@00114000"; | |
| emicen = "/soc/emicen@10219000"; | |
| mt6358_vcore_sshub_reg = "/soc/pwrap@10026000/mt6366/mt6358regulator/buck_vcore_sshub"; | |
| vdec_gcon_base_clk = "/syscon@1602f000"; | |
| camsv6_legacy = "/camsv6_legacy@1a096000"; | |
| ap_ntc = "/thermal-zones/ap_ntc"; | |
| pdc = "/pdc"; | |
| dvfsrc_freq_opp2 = "/soc/dvfsrc@10012000/opp2"; | |
| opp_table_vdec = "/opp-table-vdec"; | |
| gpu_throttle = "/thermal-zones/gpu2/trips/trip-point@0"; | |
| atf_logger = "/atf_logger"; | |
| apmixedsys_clk = "/syscon@1000C000"; | |
| mt6358_vio18_reg = "/soc/pwrap@10026000/mt6366/mt6358regulator/ldo_vio18"; | |
| charger = "/charger"; | |
| mt6375_chg = "/soc/i2c@11017000/mt6375@34/chg"; | |
| smart_pa = "/soc/smart_pa"; | |
| lkg = "/soc/lkg@00114400"; | |
| lkginfo = "/soc/efuse@11c10000/lkg"; | |
| dvfsrc_freq_opp4 = "/soc/dvfsrc@10012000/opp4"; | |
| mipi_tx_config0 = "/soc/mipi_tx_config@11f60000"; | |
| mmc0_pins_uhs = "/soc/pinctrl/mmc0@0"; | |
| cpu5 = "/cpus/cpu@005"; | |
| disp_postmask0 = "/soc/disp_postmask0@1400e000"; | |
| mt6358_vrf12_reg = "/soc/pwrap@10026000/mt6366/mt6358regulator/ldo_vrf12"; | |
| keypad = "/soc/kp@10010000"; | |
| odm = "/soc/odm"; | |
| mmc0_pins_pull_down = "/soc/pinctrl/mmc0@1"; | |
| mt6358_vxo22_reg = "/soc/pwrap@10026000/mt6366/mt6358regulator/ldo_vxo22"; | |
| dvfsrc_freq_opp0 = "/soc/dvfsrc@10012000/opp0"; | |
| cpu4 = "/cpus/cpu@004"; | |
| rt5133_eint = "/soc/odm/rt5133_eint"; | |
| system_pll = "/cpus/idle-states/system_pll"; | |
| camsys_rawb_legacy = "/camsys_rawb_legacy@1a06f000"; | |
| mdpsys_config_clk = "/syscon@1f000000"; | |
| eint = "/soc/apirq@1000b000"; | |
| pe2 = "/pe2"; | |
| cpuoff_l = "/cpus/idle-states/cpuoff_l"; | |
| rt5133_gpio3 = "/soc/odm/rt5133-gpio3"; | |
| }; | |
| tinysys_mbox@10451000 { | |
| #mbox-cells = <0x01>; | |
| compatible = "mediatek,tinysys_mbox"; | |
| shmem = <0x15 0x16>; | |
| reg = <0x00 0x10451000 0x00 0x1000 0x00 0x10461000 0x00 0x1000>; | |
| phandle = <0x14>; | |
| interrupts = <0x00 0x114 0x04 0x00 0x00 0x115 0x04 0x00>; | |
| }; | |
| camsv7_legacy@1a097000 { | |
| mediatek,larb = <0x44>; | |
| compatible = "mediatek,camsv7_legacy"; | |
| dma-ranges = <0x02 0x00 0x02 0x00 0x01 0x00>; | |
| reg = <0x00 0x1a097000 0x00 0x1000>; | |
| phandle = <0x105>; | |
| interrupts = <0x00 0x16f 0x04 0x00>; | |
| }; | |
| syscon@14000000 { | |
| compatible = "mediatek,mt6789-mmsys\0syscon"; | |
| reg = <0x00 0x14000000 0x00 0x1000>; | |
| phandle = <0x35>; | |
| #clock-cells = <0x01>; | |
| }; | |
| pdc { | |
| vsys_watt = <0x4c4b40>; | |
| dual_polling_ieoc = <0x6ddd0>; | |
| vbat_threshold = <0x1036>; | |
| slave_mivr_diff = <0x186a0>; | |
| gauge = <0xd3>; | |
| compatible = "mediatek,charger,pd"; | |
| ibus_err = <0x0e>; | |
| min_charger_voltage = <0x4630c0>; | |
| pd_vbus_upper_bound = <0xb71b00>; | |
| dcs_chg2_charger_current = <0x16e360>; | |
| dcs_input_current = <0x30d400>; | |
| sc_input_current = <0x30d400>; | |
| phandle = <0x1a8>; | |
| pd_vbus_low_bound = <0x4c4b40>; | |
| sc_charger_current = <0x2dc6c0>; | |
| dcs_chg1_charger_current = <0x16e360>; | |
| pd_stop_battery_soc = <0x50>; | |
| }; | |
| atf_logger { | |
| compatible = "mediatek,tfa_debug"; | |
| phandle = <0xef>; | |
| }; | |
| charger { | |
| min_charger_voltage_2 = <0x401640>; | |
| temp_t4_thres = <0x32>; | |
| disable_aicl; | |
| jeita_temp_t2_to_t3_cv = <0x423920>; | |
| temp_t4_thres_minus_x_degree = <0x2f>; | |
| jeita_temp_below_t0_cv = <0x3da540>; | |
| gauge = <0xd3>; | |
| compatible = "mediatek,charger"; | |
| temp_t0_thres_plus_x_degree = <0x00>; | |
| temp_t3_thres = <0x2d>; | |
| battery_cv = <0x426030>; | |
| jeita_temp_t0_to_t1_cv = <0x3da540>; | |
| jeita_temp_t3_to_t4_cv = <0x40b280>; | |
| algorithm_name = "Basic"; | |
| min_charger_voltage = <0x4630c0>; | |
| charger_configuration = <0x00>; | |
| ac_charger_input_current = <0x30d400>; | |
| temp_t3_thres_minus_x_degree = <0x27>; | |
| min_charge_temp = <0x00>; | |
| min_charger_voltage_1 = <0x432380>; | |
| enable_min_charge_temp; | |
| ac_charger_current = <0x1f47d0>; | |
| usb_charger_current = <0x7a120>; | |
| temp_t2_thres = <0x0a>; | |
| min_charge_temp_plus_x_degree = <0x06>; | |
| max_dmivr_charger_current = <0x1b7740>; | |
| phandle = <0x1ab>; | |
| jeita_temp_above_t4_cv = <0x40b280>; | |
| bootmode = <0x50>; | |
| temp_neg_10_thres = <0x00>; | |
| temp_t2_thres_plus_x_degree = <0x10>; | |
| enable_dynamic_mivr; | |
| max_charge_temp_minus_x_degree = <0x2f>; | |
| temp_t1_thres = <0x00>; | |
| jeita_temp_t1_to_t2_cv = <0x40b280>; | |
| charging_host_charger_current = <0x16e360>; | |
| temp_t1_thres_plus_x_degree = <0x06>; | |
| temp_t0_thres = <0x00>; | |
| max_charger_voltage = <0x632ea0>; | |
| max_charge_temp = <0x32>; | |
| charger = <0x53>; | |
| }; | |
| syscon@13fbf000 { | |
| compatible = "mediatek,mt6789-mfg\0syscon"; | |
| reg = <0x00 0x13fbf000 0x00 0x1000>; | |
| phandle = <0x8c>; | |
| #clock-cells = <0x01>; | |
| }; | |
| thermal-zones { | |
| phandle = <0xe4>; | |
| soc2 { | |
| polling-delay-passive = <0x00>; | |
| polling-delay = <0x00>; | |
| thermal-sensors = <0x1b 0x0c>; | |
| }; | |
| camera_sub { | |
| polling-delay-passive = <0x00>; | |
| polling-delay = <0x3e8>; | |
| phandle = <0x1f4>; | |
| thermal-sensors = <0x1cb>; | |
| }; | |
| cpu_big4 { | |
| polling-delay-passive = <0x00>; | |
| polling-delay = <0x00>; | |
| thermal-sensors = <0x1b 0x08>; | |
| }; | |
| soc_max { | |
| polling-delay-passive = <0x00>; | |
| polling-delay = <0x00>; | |
| thermal-sensors = <0x1b 0x00>; | |
| trips { | |
| soc_max_crit@0 { | |
| hysteresis = <0x7d0>; | |
| temperature = <0x1bb5c>; | |
| phandle = <0xe5>; | |
| type = "critical"; | |
| }; | |
| }; | |
| }; | |
| pmic6366_bk2 { | |
| polling-delay-passive = <0x00>; | |
| polling-delay = <0x00>; | |
| thermal-sensors = <0x20 0x02>; | |
| }; | |
| camera_main { | |
| polling-delay-passive = <0x00>; | |
| polling-delay = <0x3e8>; | |
| phandle = <0x1f3>; | |
| thermal-sensors = <0x1ca>; | |
| }; | |
| cpu_big3 { | |
| polling-delay-passive = <0x00>; | |
| polling-delay = <0x00>; | |
| thermal-sensors = <0x1b 0x07>; | |
| }; | |
| soc1 { | |
| polling-delay-passive = <0x00>; | |
| polling-delay = <0x00>; | |
| thermal-sensors = <0x1b 0x0b>; | |
| }; | |
| gpu2 { | |
| polling-delay-passive = <0x0c>; | |
| polling-delay = <0x1f4>; | |
| thermal-sensors = <0x1b 0x09>; | |
| trips { | |
| trip-point@0 { | |
| hysteresis = <0x7d0>; | |
| temperature = <0x14c08>; | |
| phandle = <0x1c>; | |
| type = "passive"; | |
| }; | |
| }; | |
| cooling-maps { | |
| map0 { | |
| trip = <0x1c>; | |
| contribution = <0x400>; | |
| cooling-device = <0x1d 0xffffffff 0xffffffff>; | |
| }; | |
| }; | |
| }; | |
| gpu1 { | |
| polling-delay-passive = <0x00>; | |
| polling-delay = <0x00>; | |
| thermal-sensors = <0x1b 0x0a>; | |
| }; | |
| pmic6366_bk1 { | |
| polling-delay-passive = <0x00>; | |
| polling-delay = <0x00>; | |
| thermal-sensors = <0x20 0x01>; | |
| }; | |
| cpu_big1 { | |
| polling-delay-passive = <0x00>; | |
| polling-delay = <0x00>; | |
| thermal-sensors = <0x1b 0x05>; | |
| }; | |
| cpu_little1 { | |
| polling-delay-passive = <0x00>; | |
| polling-delay = <0x00>; | |
| thermal-sensors = <0x1b 0x01>; | |
| }; | |
| pmic6366_bk3 { | |
| polling-delay-passive = <0x00>; | |
| polling-delay = <0x00>; | |
| thermal-sensors = <0x20 0x03>; | |
| }; | |
| consys { | |
| polling-delay-passive = <0x00>; | |
| polling-delay = <0x00>; | |
| thermal-sensors = <0x21>; | |
| }; | |
| cpu_big2 { | |
| polling-delay-passive = <0x00>; | |
| polling-delay = <0x00>; | |
| thermal-sensors = <0x1b 0x06>; | |
| }; | |
| md { | |
| polling-delay-passive = <0x00>; | |
| polling-delay = <0x00>; | |
| thermal-sensors = <0x1b 0x0d>; | |
| }; | |
| cpu_little4 { | |
| polling-delay-passive = <0x00>; | |
| polling-delay = <0x00>; | |
| thermal-sensors = <0x1b 0x04>; | |
| }; | |
| pmic6366_pmu { | |
| polling-delay-passive = <0x00>; | |
| polling-delay = <0x00>; | |
| thermal-sensors = <0x20 0x00>; | |
| }; | |
| ltepa_ntc { | |
| polling-delay-passive = <0x00>; | |
| polling-delay = <0x00>; | |
| phandle = <0xe7>; | |
| thermal-sensors = <0x1f>; | |
| }; | |
| camera_main_two { | |
| polling-delay-passive = <0x00>; | |
| polling-delay = <0x3e8>; | |
| phandle = <0x1f5>; | |
| thermal-sensors = <0x1cc>; | |
| }; | |
| ap_ntc { | |
| polling-delay-passive = <0x00>; | |
| polling-delay = <0x00>; | |
| phandle = <0xe6>; | |
| thermal-sensors = <0x1e>; | |
| }; | |
| cpu_little3 { | |
| polling-delay-passive = <0x00>; | |
| polling-delay = <0x00>; | |
| thermal-sensors = <0x1b 0x03>; | |
| }; | |
| cpu_little2 { | |
| polling-delay-passive = <0x00>; | |
| polling-delay = <0x00>; | |
| thermal-sensors = <0x1b 0x02>; | |
| }; | |
| }; | |
| camsv2_legacy@1a092000 { | |
| mediatek,larb = <0x44>; | |
| compatible = "mediatek,camsv2_legacy"; | |
| dma-ranges = <0x02 0x00 0x02 0x00 0x01 0x00>; | |
| reg = <0x00 0x1a092000 0x00 0x1000>; | |
| phandle = <0x100>; | |
| interrupts = <0x00 0x167 0x04 0x00>; | |
| }; | |
| pe2 { | |
| dual_polling_ieoc = <0x6ddd0>; | |
| vbat_threshold = <0x1036>; | |
| ta_start_battery_soc = <0x00>; | |
| slave_mivr_diff = <0x186a0>; | |
| gauge = <0xd3>; | |
| compatible = "mediatek,charger,pe2"; | |
| vbat_cable_imp_threshold = <0x3b8260>; | |
| min_charger_voltage = <0x4630c0>; | |
| ta_stop_battery_soc = <0x55>; | |
| dcs_chg2_charger_current = <0x16e360>; | |
| dcs_input_current = <0x30d400>; | |
| sc_input_current = <0x30d400>; | |
| phandle = <0x1a7>; | |
| cable_imp_threshold = <0x2bb>; | |
| sc_charger_current = <0x2dc6c0>; | |
| dcs_chg1_charger_current = <0x16e360>; | |
| pe20_ichg_level_threshold = <0xf4240>; | |
| }; | |
| }; |
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