kn0 SpiralBL0CK

Visualizing the RISC-V Instruction Set

Earlier today, I came across the blog post "Visualizing the ARM64 Instruction Set" and got inspired to give it a shot my self.

After hacking together a quick script and fiddling with the bit order and colors for way too long, I managed to create a decent visualization of the RISC-V instruction encoding. You can find my code below.

The following graphics cover the 64-bit part of the RISC-V ISA, including all ratified 64-bit extensions, with opcodes extracted from the riscv/riscv-opcodes repo.

I mapped the opcodes to 2D coordinates with a Morton space-filling curve.

Using capset

// Thanks to @pqlqpql
#include <linux/io_uring.h>
#include <sys/capability.h>
#include <sys/syscall.h>

struct user_cap_data_struct {
    uint32_t effective;
    uint32_t permitted;

Using capset

// Thanks to @pqlqpql
#include <linux/io_uring.h>
#include <sys/capability.h>
#include <sys/syscall.h>

struct user_cap_data_struct {
    uint32_t effective;
    uint32_t permitted;

	git revert e85682585ab27a3c0593c403b892190c52009960

	Compiled using the following flags:

	$ CC=clang-8 CXX=clang++-8 CCFLAGS="-fprofile-instr-generate -fcoverage-mapping" CXXFLAGS="-fprofile-instr-generate -fcoverage-mapping" ./configure --with-sanitizer=address --disable-xcb
	$ ASAN_OPTIONS=detect_leaks=0 make -j4