Testing done using a Canon EOS 600D and a Canon EF-S18-55mm f/3.5-5.6 IS II.

Pinout:

1. VBAT
2. P-GND | Same strip of metal
3. P-GND | on the lens side
4. VDD
5. DCL
6. DLC
7. LCLK
8. D_GND

VDD is nominally 5V. VBAT seems to also be ~5V (others report 6V).

VDD is always active (even with the camera off, if it has been powered on at least once). When the camera turns on, VDD increases slightly (standby power vs. active regulator?)

The data lines are idle high and weakly pulled up by the camera. However, the drivers are not open drain (to get better rise times).

The protocol is basically a variant of SPI with CPOL=1,CPHA=1. There is no framing or CS signal, which complicates parsing, and there is an additional variable length ACK clock pulse driven by the lens (kind of like I²C clock stretching).

Default clock period is 13µs (6.5µs per half cycle) = 77 kHz This decreases to 2µs for nwer lenses (1µs per half cycle) = 500 kHz Intended duty cycle seems to be 50% (fast mode seems to be 0.8µs low / 1.2µs high, but this is likely just an analog effect).

Power-on timing:

• 1µs low glitch on DCL (?)
• 42µs delay (?)
• Single 6.5µs low pulse on DCL (does this serve a purpose?)
• 103µs delay
• First three byte cycles:
  • C 00 L ff [TX 89us ACK 14us BUSY 2165us] <- note long BUSY period
  • C 0a L aa [TX 89us ACK 14us BUSY 4us]
  • C 00 L aa [TX 89us ACK 14us BUSY 4us] <- VBAT turned on by camera during the lens ACK/BUSY pulse

Command byte timing:

• Camera drives DCL at a random value for ~18µs (slow mode) or ~4µs (fast mode)
  • This seems to usually be whatever the last bit of the previous command was, but not always consistent.
• Each bit is driven (by both camera and lens) on the falling edge of LCLK, and sampled on the rising edge.
• Camera drives DCL high (or stops driving?) and stops driving LCLK 1µs after the last rising edge of LCLK (this is half a cycle in fast mode, but much shorter than half a cycle in slow mode).
• Lens releases DLC ~4.3µs after the last rising edge of LCLK
• Lens drives LCLK low ~14µs after the last rising edge of LCLK (ACK/BUSY)
• ACK/BUSY pulse seems to last at least 4µs but may be much longer
• Gap between bytes (rising edge of LCLK ACK/BUSY to first falling edge of LCLK) is at least 120µs in slow mode and at least 18µs in fast mode.

Note that slow/fast mode only changes the camera timings. The lens always behaves the same way.