-- File: top_structuraldesign.vhd
-- Generated by MyHDL 1.0dev
-- Date: Fri Nov 24 20:27:59 2017

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;

use work.pck_myhdl_10.all;

entity top_structuraldesign is
	port(
		Clk      : in  std_logic;
		Reset    : in  std_logic;
		DataIn0  : in  unsigned(7 downto 0);
		ValidIn0 : in  std_logic;
		DataIn1  : in  unsigned(7 downto 0);
		ValidIn1 : in  std_logic;
		DataIn2  : in  unsigned(7 downto 0);
		ValidIn2 : in  std_logic;
		DataIn3  : in  unsigned(7 downto 0);
		ValidIn3 : in  std_logic;
		ReadyOut : in  std_logic;
		ReadyIn0 : out std_logic;
		ReadyIn1 : out std_logic;
		ReadyIn2 : out std_logic;
		ReadyIn3 : out std_logic;
		DataOut  : out unsigned(7 downto 0);
		ValidOut : out std_logic
	);
end entity top_structuraldesign;

architecture MyHDL of top_structuraldesign is

	type t_enum_buffer_state_1 is (
		BUF_FREE,
		BUF_TAKEN
	);
	type t_enum_buffer_state_2 is (
		BUF_FREE,
		BUF_TAKEN
	);
	type t_enum_buffer_state_3 is (
		BUF_FREE,
		BUF_TAKEN
	);
	type t_enum_buffer_state_4 is (
		BUF_FREE,
		BUF_TAKEN
	);
	type t_enum_buffer_state_5 is (
		BUF_FREE,
		BUF_TAKEN
	);
	signal rtl_1_muxreadyin1         : std_logic;
	signal rtl_1_buforeadyin         : std_logic;
	signal rtl_1_muxreadyin3         : std_logic;
	signal rtl_1_muxreadyin2         : std_logic;
	signal rtl_1_muxreadyin0         : std_logic;
	signal rtl_1_rtl_1_self_ValidOut : std_logic;
	signal rtl_1_rtl_1_smn           : t_enum_buffer_state_1;
	signal rtl_1_rtl_1_ldbuf         : std_logic;
	signal rtl_1_rtl_1_smp           : t_enum_buffer_state_1;
	signal rtl_1_rtl_1_self_DataOut  : unsigned(7 downto 0);
	signal rtl_1_rtl_1_self_ValidOut : std_logic;
	signal rtl_1_rtl_1_smn           : t_enum_buffer_state_2;
	signal rtl_1_rtl_1_ldbuf         : std_logic;
	signal rtl_1_rtl_1_smp           : t_enum_buffer_state_2;
	signal rtl_1_rtl_1_self_DataOut  : unsigned(7 downto 0);
	signal rtl_1_rtl_1_self_ValidOut : std_logic;
	signal rtl_1_rtl_1_smn           : t_enum_buffer_state_3;
	signal rtl_1_rtl_1_ldbuf         : std_logic;
	signal rtl_1_rtl_1_smp           : t_enum_buffer_state_3;
	signal rtl_1_rtl_1_self_DataOut  : unsigned(7 downto 0);
	signal rtl_1_rtl_1_self_ValidOut : std_logic;
	signal rtl_1_rtl_1_smn           : t_enum_buffer_state_4;
	signal rtl_1_rtl_1_ldbuf         : std_logic;
	signal rtl_1_rtl_1_smp           : t_enum_buffer_state_4;
	signal rtl_1_rtl_1_self_DataOut  : unsigned(7 downto 0);
	signal rtl_1_rtl_1_self_ValidOut : std_logic;
	signal rtl_1_rtl_1_self_DataOut  : unsigned(7 downto 0);
	signal rtl_1_rtl_1_smn           : t_enum_buffer_state_5;
	signal rtl_1_rtl_1_ldbuf         : std_logic;
	signal rtl_1_rtl_1_smp           : t_enum_buffer_state_5;

begin

	-- Buffer: the combinatorial part of the state-machine 
	TOP_STRUCTURALDESIGN_RTL_1_RTL_1_SMCOMB : process(rtl_1_muxreadyin0, ValidIn0, rtl_1_rtl_1_smp) is
	begin
		ReadyIn0                  <= '0';
		rtl_1_rtl_1_self_ValidOut <= '0';
		rtl_1_rtl_1_ldbuf         <= '0';
		case rtl_1_rtl_1_smp is
			when BUF_FREE =>
				ReadyIn0 <= '1';
				if bool(ValidIn0) then
					rtl_1_rtl_1_smn   <= BUF_TAKEN;
					rtl_1_rtl_1_ldbuf <= '1';
				else
					rtl_1_rtl_1_smn <= BUF_FREE;
				end if;
			when others =>              -- BUF_TAKEN
				rtl_1_rtl_1_self_ValidOut <= '1';
				if bool(rtl_1_muxreadyin0) then
					ReadyIn0 <= '1';
					if bool(ValidIn0) then
						rtl_1_rtl_1_smn   <= BUF_TAKEN;
						rtl_1_rtl_1_ldbuf <= '1';
					else
						rtl_1_rtl_1_smn <= BUF_FREE;
					end if;
				else
					rtl_1_rtl_1_smn <= BUF_TAKEN;
				end if;
		end case;
	end process TOP_STRUCTURALDESIGN_RTL_1_RTL_1_SMCOMB;

	-- Buffer: the synchronous part of the state-machine 
	TOP_STRUCTURALDESIGN_RTL_1_RTL_1_SMSYNC : process(Clk, Reset) is
	begin
		if (Reset = '1') then
			rtl_1_rtl_1_smp <= BUF_FREE;
		elsif rising_edge(Clk) then
			rtl_1_rtl_1_smp <= rtl_1_rtl_1_smn;
		end if;
	end process TOP_STRUCTURALDESIGN_RTL_1_RTL_1_SMSYNC;

	-- Buffer: the registered part of the state-machine 
	TOP_STRUCTURALDESIGN_RTL_1_RTL_1_SMREG : process(Clk) is
	begin
		if rising_edge(Clk) then
			if bool(rtl_1_rtl_1_ldbuf) then
				rtl_1_rtl_1_self_DataOut <= DataIn0;
			end if;
		end if;
	end process TOP_STRUCTURALDESIGN_RTL_1_RTL_1_SMREG;

	-- Buffer: the combinatorial part of the state-machine 
	TOP_STRUCTURALDESIGN_RTL_1_RTL_1_SMCOMB : process(rtl_1_muxreadyin1, ValidIn1, rtl_1_rtl_1_smp) is
	begin
		ReadyIn1                  <= '0';
		rtl_1_rtl_1_self_ValidOut <= '0';
		rtl_1_rtl_1_ldbuf         <= '0';
		case rtl_1_rtl_1_smp is
			when BUF_FREE =>
				ReadyIn1 <= '1';
				if bool(ValidIn1) then
					rtl_1_rtl_1_smn   <= BUF_TAKEN;
					rtl_1_rtl_1_ldbuf <= '1';
				else
					rtl_1_rtl_1_smn <= BUF_FREE;
				end if;
			when others =>              -- BUF_TAKEN
				rtl_1_rtl_1_self_ValidOut <= '1';
				if bool(rtl_1_muxreadyin1) then
					ReadyIn1 <= '1';
					if bool(ValidIn1) then
						rtl_1_rtl_1_smn   <= BUF_TAKEN;
						rtl_1_rtl_1_ldbuf <= '1';
					else
						rtl_1_rtl_1_smn <= BUF_FREE;
					end if;
				else
					rtl_1_rtl_1_smn <= BUF_TAKEN;
				end if;
		end case;
	end process TOP_STRUCTURALDESIGN_RTL_1_RTL_1_SMCOMB;

	-- Buffer: the synchronous part of the state-machine 
	TOP_STRUCTURALDESIGN_RTL_1_RTL_1_SMSYNC : process(Clk, Reset) is
	begin
		if (Reset = '1') then
			rtl_1_rtl_1_smp <= BUF_FREE;
		elsif rising_edge(Clk) then
			rtl_1_rtl_1_smp <= rtl_1_rtl_1_smn;
		end if;
	end process TOP_STRUCTURALDESIGN_RTL_1_RTL_1_SMSYNC;

	-- Buffer: the registered part of the state-machine 
	TOP_STRUCTURALDESIGN_RTL_1_RTL_1_SMREG : process(Clk) is
	begin
		if rising_edge(Clk) then
			if bool(rtl_1_rtl_1_ldbuf) then
				rtl_1_rtl_1_self_DataOut <= DataIn1;
			end if;
		end if;
	end process TOP_STRUCTURALDESIGN_RTL_1_RTL_1_SMREG;

	-- Buffer: the combinatorial part of the state-machine 
	TOP_STRUCTURALDESIGN_RTL_1_RTL_1_SMCOMB : process(rtl_1_muxreadyin2, ValidIn2, rtl_1_rtl_1_smp) is
	begin
		ReadyIn2                  <= '0';
		rtl_1_rtl_1_self_ValidOut <= '0';
		rtl_1_rtl_1_ldbuf         <= '0';
		case rtl_1_rtl_1_smp is
			when BUF_FREE =>
				ReadyIn2 <= '1';
				if bool(ValidIn2) then
					rtl_1_rtl_1_smn   <= BUF_TAKEN;
					rtl_1_rtl_1_ldbuf <= '1';
				else
					rtl_1_rtl_1_smn <= BUF_FREE;
				end if;
			when others =>              -- BUF_TAKEN
				rtl_1_rtl_1_self_ValidOut <= '1';
				if bool(rtl_1_muxreadyin2) then
					ReadyIn2 <= '1';
					if bool(ValidIn2) then
						rtl_1_rtl_1_smn   <= BUF_TAKEN;
						rtl_1_rtl_1_ldbuf <= '1';
					else
						rtl_1_rtl_1_smn <= BUF_FREE;
					end if;
				else
					rtl_1_rtl_1_smn <= BUF_TAKEN;
				end if;
		end case;
	end process TOP_STRUCTURALDESIGN_RTL_1_RTL_1_SMCOMB;

	-- Buffer: the synchronous part of the state-machine 
	TOP_STRUCTURALDESIGN_RTL_1_RTL_1_SMSYNC : process(Clk, Reset) is
	begin
		if (Reset = '1') then
			rtl_1_rtl_1_smp <= BUF_FREE;
		elsif rising_edge(Clk) then
			rtl_1_rtl_1_smp <= rtl_1_rtl_1_smn;
		end if;
	end process TOP_STRUCTURALDESIGN_RTL_1_RTL_1_SMSYNC;

	-- Buffer: the registered part of the state-machine 
	TOP_STRUCTURALDESIGN_RTL_1_RTL_1_SMREG : process(Clk) is
	begin
		if rising_edge(Clk) then
			if bool(rtl_1_rtl_1_ldbuf) then
				rtl_1_rtl_1_self_DataOut <= DataIn2;
			end if;
		end if;
	end process TOP_STRUCTURALDESIGN_RTL_1_RTL_1_SMREG;

	-- Buffer: the combinatorial part of the state-machine 
	TOP_STRUCTURALDESIGN_RTL_1_RTL_1_SMCOMB : process(rtl_1_muxreadyin3, ValidIn3, rtl_1_rtl_1_smp) is
	begin
		ReadyIn3                  <= '0';
		rtl_1_rtl_1_self_ValidOut <= '0';
		rtl_1_rtl_1_ldbuf         <= '0';
		case rtl_1_rtl_1_smp is
			when BUF_FREE =>
				ReadyIn3 <= '1';
				if bool(ValidIn3) then
					rtl_1_rtl_1_smn   <= BUF_TAKEN;
					rtl_1_rtl_1_ldbuf <= '1';
				else
					rtl_1_rtl_1_smn <= BUF_FREE;
				end if;
			when others =>              -- BUF_TAKEN
				rtl_1_rtl_1_self_ValidOut <= '1';
				if bool(rtl_1_muxreadyin3) then
					ReadyIn3 <= '1';
					if bool(ValidIn3) then
						rtl_1_rtl_1_smn   <= BUF_TAKEN;
						rtl_1_rtl_1_ldbuf <= '1';
					else
						rtl_1_rtl_1_smn <= BUF_FREE;
					end if;
				else
					rtl_1_rtl_1_smn <= BUF_TAKEN;
				end if;
		end case;
	end process TOP_STRUCTURALDESIGN_RTL_1_RTL_1_SMCOMB;

	-- Buffer: the synchronous part of the state-machine 
	TOP_STRUCTURALDESIGN_RTL_1_RTL_1_SMSYNC : process(Clk, Reset) is
	begin
		if (Reset = '1') then
			rtl_1_rtl_1_smp <= BUF_FREE;
		elsif rising_edge(Clk) then
			rtl_1_rtl_1_smp <= rtl_1_rtl_1_smn;
		end if;
	end process TOP_STRUCTURALDESIGN_RTL_1_RTL_1_SMSYNC;

	-- Buffer: the registered part of the state-machine 
	TOP_STRUCTURALDESIGN_RTL_1_RTL_1_SMREG : process(Clk) is
	begin
		if rising_edge(Clk) then
			if bool(rtl_1_rtl_1_ldbuf) then
				rtl_1_rtl_1_self_DataOut <= DataIn3;
			end if;
		end if;
	end process TOP_STRUCTURALDESIGN_RTL_1_RTL_1_SMREG;

	TOP_STRUCTURALDESIGN_RTL_1_RTL_1_MUX : process(rtl_1_buforeadyin, rtl_1_rtl_1_self_DataOut, rtl_1_rtl_1_self_ValidOut) is
	begin
		rtl_1_muxreadyin0         <= '0';
		rtl_1_muxreadyin1         <= '0';
		rtl_1_muxreadyin2         <= '0';
		rtl_1_muxreadyin3         <= '0';
		rtl_1_rtl_1_self_ValidOut <= '0';
		rtl_1_rtl_1_self_DataOut  <= to_unsigned(0, 8);
		if bool(rtl_1_rtl_1_self_ValidOut) then
			rtl_1_rtl_1_self_ValidOut <= '1';
			rtl_1_rtl_1_self_DataOut  <= rtl_1_rtl_1_self_DataOut;
			if bool(rtl_1_buforeadyin) then
				rtl_1_muxreadyin0 <= '1';
			end if;
		elsif bool(rtl_1_rtl_1_self_ValidOut) then
			rtl_1_rtl_1_self_ValidOut <= '1';
			rtl_1_rtl_1_self_DataOut  <= rtl_1_rtl_1_self_DataOut;
			if bool(rtl_1_buforeadyin) then
				rtl_1_muxreadyin1 <= '1';
			end if;
		elsif bool(rtl_1_rtl_1_self_ValidOut) then
			rtl_1_rtl_1_self_ValidOut <= '1';
			rtl_1_rtl_1_self_DataOut  <= rtl_1_rtl_1_self_DataOut;
			if bool(rtl_1_buforeadyin) then
				rtl_1_muxreadyin2 <= '1';
			end if;
		elsif bool(rtl_1_rtl_1_self_ValidOut) then
			rtl_1_rtl_1_self_ValidOut <= '1';
			rtl_1_rtl_1_self_DataOut  <= rtl_1_rtl_1_self_DataOut;
			if bool(rtl_1_buforeadyin) then
				rtl_1_muxreadyin3 <= '1';
			end if;
		end if;
	end process TOP_STRUCTURALDESIGN_RTL_1_RTL_1_MUX;

	-- Buffer: the combinatorial part of the state-machine 
	TOP_STRUCTURALDESIGN_RTL_1_RTL_1_SMCOMB : process(ReadyOut, rtl_1_rtl_1_self_ValidOut, rtl_1_rtl_1_smp) is
	begin
		rtl_1_buforeadyin <= '0';
		ValidOut          <= '0';
		rtl_1_rtl_1_ldbuf <= '0';
		case rtl_1_rtl_1_smp is
			when BUF_FREE =>
				rtl_1_buforeadyin <= '1';
				if bool(rtl_1_rtl_1_self_ValidOut) then
					rtl_1_rtl_1_smn   <= BUF_TAKEN;
					rtl_1_rtl_1_ldbuf <= '1';
				else
					rtl_1_rtl_1_smn <= BUF_FREE;
				end if;
			when others =>              -- BUF_TAKEN
				ValidOut <= '1';
				if bool(ReadyOut) then
					rtl_1_buforeadyin <= '1';
					if bool(rtl_1_rtl_1_self_ValidOut) then
						rtl_1_rtl_1_smn   <= BUF_TAKEN;
						rtl_1_rtl_1_ldbuf <= '1';
					else
						rtl_1_rtl_1_smn <= BUF_FREE;
					end if;
				else
					rtl_1_rtl_1_smn <= BUF_TAKEN;
				end if;
		end case;
	end process TOP_STRUCTURALDESIGN_RTL_1_RTL_1_SMCOMB;

	-- Buffer: the synchronous part of the state-machine 
	TOP_STRUCTURALDESIGN_RTL_1_RTL_1_SMSYNC : process(Clk, Reset) is
	begin
		if (Reset = '1') then
			rtl_1_rtl_1_smp <= BUF_FREE;
		elsif rising_edge(Clk) then
			rtl_1_rtl_1_smp <= rtl_1_rtl_1_smn;
		end if;
	end process TOP_STRUCTURALDESIGN_RTL_1_RTL_1_SMSYNC;

	-- Buffer: the registered part of the state-machine 
	TOP_STRUCTURALDESIGN_RTL_1_RTL_1_SMREG : process(Clk) is
	begin
		if rising_edge(Clk) then
			if bool(rtl_1_rtl_1_ldbuf) then
				DataOut <= rtl_1_rtl_1_self_DataOut;
			end if;
		end if;
	end process TOP_STRUCTURALDESIGN_RTL_1_RTL_1_SMREG;

end architecture MyHDL;