--- LPC43xx.svd.orig 2017-08-03 20:37:12.501824574 -0700 +++ LPC43xx.svd 2017-08-03 22:25:24.933731557 -0700 @@ -142,82 +142,82 @@ ENUM - RISING_EDGES_ON_INPU + INPUT_0_RISING_EDGE Rising edges on input 0. 0x0 - FALLING_EDGES_ON_INP + INPUT_0_FALLING_EDGE Falling edges on input 0. 0x1 - RISING_EDGES_ON_INPU + INPUT_1_RISING_EDGE Rising edges on input 1. 0x2 - FALLING_EDGES_ON_INP + INPUT_1_FALLING_EDGE Falling edges on input 1. 0x3 - RISING_EDGES_ON_INPU + INPUT_2_RISING_EDGE Rising edges on input 2. 0x4 - FALLING_EDGES_ON_INP + INPUT_2_FALLING_EDGE Falling edges on input 2. 0x5 - RISING_EDGES_ON_INPU + INPUT_3_RISING_EDGE Rising edges on input 3. 0x6 - FALLING_EDGES_ON_INP + INPUT_3_FALLING_EDGE Falling edges on input 3. 0x7 - RISING_EDGES_ON_INPU + INPUT_4_RISING_EDGE Rising edges on input 4. 0x8 - FALLING_EDGES_ON_INP + INPUT_4_FALLING_EDGE Falling edges on input 4. 0x9 - RISING_EDGES_ON_INPU + INPUT_5_RISING_EDGE Rising edges on input 5. 0xA - FALLING_EDGES_ON_INP + INPUT_5_FALLING_EDGE Falling edges on input 5. 0xB - RISING_EDGES_ON_INPU + INPUT_6_RISING_EDGE Rising edges on input 6. 0xC - FALLING_EDGES_ON_INP + INPUT_6_FALLING_EDGE Falling edges on input 6. 0xD - RISING_EDGES_ON_INPU + INPUT_7_RISING_EDGE Rising edges on input 7. 0xE - FALLING_EDGES_ON_INP + INPUT_7_FALLING_EDGE Falling edges on input 7. 0xF @@ -3678,7 +3678,7 @@ ENUM - DISABLED__DEFAULT_ + DISABLED Disabled (default). Disabling the DMA Controller reduces power consumption. 0 @@ -4157,12 +4157,12 @@ ENUM - THE_DESTINATION_ADDR + AFTER_XFER_NO_INC The destination address is not incremented after each transfer. 0 - THE_DESTINATION_ADDR + AFTER_XFER_INC The destination address is incremented after each transfer. 1 @@ -4229,12 +4229,12 @@ ENUM - THE_TERMINAL_COUNT_I + TC_INT_DISABLED The terminal count interrupt is disabled. 0 - THE_TERMINAL_COUNT_I + TC_INT_ENABLED The terminal count interrupt is enabled. 1 @@ -4278,82 +4278,82 @@ ENUM - SOURCE_EQ_SPIFI + SPIFI_SCTMATCH2_SGPIO14_TIMER3MATCH1 Source = SPIFI 0x0 - SOURCE_EQ_TIMER_0_MAT + TIMER0MATCH0_USART0TX_AESIN Source = Timer 0 match 0/UART0 transmit 0x1 - SOURCE_EQ_TIMER_0_MAT + TIMER0MATCH1_USART0RX_AESOUT Source = Timer 0 match 1/UART0 receive 0x2 - SOURCE_EQ_TIMER_1_MAT + TIMER1MATCH0_UART1TX_I2S1DMAREQ1_SSP1TX Source = Timer 1 match 0/UART1 transmit 0x3 - SOURCE_EQ_TIMER_1_MAT + TIMER1MATCH1_UART1RX_I2S1DMAREQ2_SSP1RX Source = Timer 1 match 1/UART 1 receive 0x4 - SOURCE_EQ_TIMER_2_MAT + TIMER2MATCH0_USART2TX_SSP1TX_SGPIO15 Source = Timer 2 match 0/UART 2 transmit 0x5 - SOURCE_EQ_TIMER_2_MAT + TIMER2MATCH1_USART2RX_SSP1RX_SGPIO14 Source = Timer 2 match 1/UART 2 receive 0x6 - SOURCE_EQ_TIMER_3_MAT + TIMER3MATCH0_UART3TX_SCTDMAREQ0_ADCHSWR Source = Timer 3 match 0/UART3 transmit/SCT DMA request 0 0x7 - SOURCE_EQ_TIMER_3_MAT + TIMER3MATCH1_UART3RX_SCTDMAREQ1_ADCHSRD Source = Timer 3 match 1/UART3 receive/SCT DMA request 1 0x8 - SOURCE_EQ_SSP0_RECEIV + SSP0RX_I2S0DMAREQ1_SCTDMAREQ1 Source = SSP0 receive/I2S channel 0 0x9 - SOURCE_EQ_SSP0_TRANSM + SSP0TX_I2S0DMAREQ2_SCTDMAREQ0 Source = SSP0 transmit/I2S channel 1 0xA - SOURCE_EQ_SSP1_RECEIV + SSP1RX_SGPIO14_USART0TX Source = SSP1 receive 0xB - SOURCE_EQ_SSP1_TRANSM + SSP1TX_SGPIO15_USART0RX Source = SSP1 transmit 0xC - SOURCE_EQ_ADC0 + ADC0_AESIN_SSP1RX_USART3RX Source = ADC0 0xD - SOURCE_EQ_ADC1 + ADC1_AESOUT_SSP1TX_USART3TX Source = ADC1 0xE - SOURCE_EQ_DAC + DAC_SCTMATCH3_SGPIO15_TIMER3MATCH0 Source = DAC 0xF @@ -4366,82 +4366,82 @@ ENUM - DESTINATION_EQ_SPIFI + SPIFI_SCTMATCH2_SGPIO14_TIMER3MATCH1 Destination = SPIFI 0x0 - DESTINATION_EQ_TIMER_ + TIMER0MATCH0_UART0TX_AESIN Destination = Timer 0 match 0/UART0 transmit 0x1 - DESTINATION_EQ_TIMER_ + TIMER0MATCH1_UART0RX_AESOUT Destination = Timer 0 match 1/UART0 receive 0x2 - DESTINATION_EQ_TIMER_ + TIMER1MATCH0_UART1TX_I2S1DMAREQ1_SSP1TX Destination = Timer 1 match 0/UART1 transmit 0x3 - DESTINATION_EQ_TIMER_ + TIMER1MATCH1_UART1RX_I2S1DMAREQ2_SSP1RX Destination = Timer 1 match 1/UART 1 receive 0x4 - DESTINATION_EQ_TIMER_ + TIMER2MATCH0_USART2TX_SSP1TX_SGPIO15 Destination = Timer 2 match 0/UART 2 transmit 0x5 - DESTINATION_EQ_TIMER_ + TIMER2MATCH1_USART2RX_SSP1RX_SGPIO14 Destination = Timer 2 match 1/UART 2 receive 0x6 - DESTINATION_EQ_TIMER_ + TIMER3MATCH0_UART3TX_SCTDMAREQ0_ADCHSWR Destination = Timer 3 match 0/UART3 transmit/SCT DMA request 0 0x7 - DESTINATION_EQ_TIMER_ + TIMER3MATCH1_UART3RX_SCTDMAREQ1_ADCHSRD Destination = Timer 3 match 1/UART3 receive/SCT DMA request 1 0x8 - DESTINATION_EQ_SSP0_R + SSP0RX_I2S0DMAREQ1_SCTDMAREQ1 Destination = SSP0 receive/I2S channel 0 0x9 - DESTINATION_EQ_SSP0_T + SSP0TX_I2S0DMAREQ2_SCTDMAREQ0 Destination = SSP0 transmit/I2S channel 1 0xA - DESTINATION_EQ_SSP1_R + SSP1RX_SGPIO14_USART0TX Destination = SSP1 receive 0xB - DESTINATION_EQ_SSP1_T + SSP1TX_SGPIO15_USART0RX Destination = SSP1 transmit 0xC - DESTINATION_EQ_ADC0 + ADC0_AESIN_SSP1RX_USART3RX Destination = ADC0 0xD - DESTINATION_EQ_ADC1 + ADC1_AESOUT_SSP1TX_USART3TX Destination = ADC1 0xE - DESTINATION_EQ_DAC + DAC_SCTMATCH3_SGPIO15_TIMER3MATCH0 Destination = DAC 0xF @@ -4454,42 +4454,42 @@ ENUM - MEMORY_TO_MEMORY + MEMORY_TO_MEMORY_DMA_CTRL Memory to memory (DMA control) 0x0 - MEMORY_TO_PERIPHERAL + MEMORY_TO_PERIPHERAL_DMA_CTRL Memory to peripheral (DMA control) 0x1 - PERIPHERAL_TO_MEMORY + PERIPHERAL_TO_MEMORY_DMA_CTRL Peripheral to memory (DMA control) 0x2 - SOURCE_PERIPHERAL_TO + PERIPHERAL_TO_PERIPHERAL_DMA_CTRL Source peripheral to destination peripheral (DMA control) 0x3 - SOURCE_PERIPHERAL_TO + PERIPHERAL_TO_PERIPHERAL_CTRL Source peripheral to destination peripheral (destination control) 0x4 - MEMORY_TO_PERIPHERAL + MEMORY_TO_PERIPHERAL_CTRL Memory to peripheral (peripheral control) 0x5 - PERIPHERAL_TO_MEMORY + PERIPHERAL_CTRL_TO_MEMORY Peripheral to memory (peripheral control) 0x6 - SOURCE_PERIPHERAL_TO + PERIPHERAL_CTRL_TO_PERIPHERAL Source peripheral to destination peripheral (source control) 0x7 @@ -8777,7 +8777,7 @@ 0 - DISABLED + ENABLED The periodic schedule status is enabled. 1 @@ -8795,7 +8795,7 @@ 0 - DISABLED + ENABLED Asynchronous schedule status is enabled. 1 @@ -9461,12 +9461,12 @@ ENUM - DEVICE_NOT_ATTACHED_ + DEVICE_NOT_ATTACHED Device not attached A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. It does not state the device being disconnected or suspended. 0 - DEVICE_ATTACHED__A_ + DEVICE_ATTACHED Device attached. A one indicates that the device successfully attached and is operating in either high-speed mode or full-speed mode as indicated by the High Speed Port bit in this register. 1 @@ -12960,12 +12960,12 @@ ENUM - DEVICE_NOT_ATTACHED_ + DEVICE_NOT_ATTACHED Device not attached A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. It does not state the device being disconnected or suspended. 0 - DEVICE_ATTACHED__A_ + DEVICE_ATTACHED Device attached. A one indicates that the device successfully attached and is operating in either high-speed mode or full-speed mode as indicated by the High Speed Port bit in this register. 1 @@ -17687,7 +17687,7 @@ ENUM - INPUT_TO_THE_EVENT_R + INPUT_TO_THE_EVENT_ROUTER Input to the event router. 0x0 @@ -17702,7 +17702,7 @@ 0x2 - INPUT_TO_THE_EVENT_R + INPUT_TO_THE_EVENT_ROUTER_3 Input to the event router. 0x3 @@ -17715,7 +17715,7 @@ ENUM - INPUT_TO_EVENT_ROUTE + INPUT_TO_EVENT_ROUTER Input to event router. 0x0 @@ -17730,7 +17730,7 @@ 0x2 - INPUT_TO_EVENT_ROUTE + INPUT_TO_EVENT_ROUTE_3 Input to event router. 0x3 @@ -37582,12 +37582,12 @@ ENUM - BREAK_INTERRUPT_STAT + INACTIVE Break interrupt status is inactive. 0 - BREAK_INTERRUPT_STAT + ACTIVE Break interrupt status is active. 1 @@ -40017,10 +40017,7 @@ - 3 - 0x4 - 18-20 - SFSP1_%s + SFSP1_18 Pin configuration register for pins P1 0x0C8 read-write @@ -40174,10 +40171,315 @@ - 3 - 0x4 - 0-2 - SFSP2_%s + SFSP1_19 + Pin configuration register for pins P1 + 0x0CC + read-write + 0 + 0xFFFFFFFF + + + MODE + Select pin function. + [2:0] + + ENUM + + FUNCTION_0_DEFAULT + Function 0 (default) + 0x0 + + + FUNCTION_1 + Function 1 + 0x1 + + + FUNCTION_2 + Function 2 + 0x2 + + + FUNCTION_3 + Function 3 + 0x3 + + + FUNCTION_4 + Function 4 + 0x4 + + + FUNCTION_5 + Function 5 + 0x5 + + + FUNCTION_6 + Function 6 + 0x6 + + + FUNCTION_7 + Function 7 + 0x7 + + + + + EPD + Enable pull-down resistor at pad. + [3:3] + + ENUM + + DISABLE_PULL_DOWN + Disable pull-down. + 0 + + + ENABLE_PULL_DOWN + Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode. + 1 + + + + + EPUN + Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset. + [4:4] + + ENUM + + ENABLE_PULL_UP + Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode. + 0 + + + DISABLE_PULL_UP + Disable pull-up. + 1 + + + + + EHS + Select Slew rate. + [5:5] + + ENUM + + SLOW_LOW_NOISE_WITH + Slow (low noise with medium speed) + 0 + + + FAST_MEDIUM_NOISE_W + Fast (medium noise with fast speed) + 1 + + + + + EZI + Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving. + [6:6] + + ENUM + + DISABLE_INPUT_BUFFER + Disable input buffer + 0 + + + ENABLE_INPUT_BUFFER + Enable input buffer + 1 + + + + + ZIF + Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz. + [7:7] + + ENUM + + ENABLE_INPUT_GLITCH + Enable input glitch filter + 0 + + + DISABLE_INPUT_GLITCH + Disable input glitch filter + 1 + + + + + RESERVED + Reserved + [31:8] + + + + + + SFSP1_20 + Pin configuration register for pins P1 + 0x0D0 + read-write + 0 + 0xFFFFFFFF + + + MODE + Select pin function. + [2:0] + + ENUM + + FUNCTION_0_DEFAULT + Function 0 (default) + 0x0 + + + FUNCTION_1 + Function 1 + 0x1 + + + FUNCTION_2 + Function 2 + 0x2 + + + FUNCTION_3 + Function 3 + 0x3 + + + FUNCTION_4 + Function 4 + 0x4 + + + FUNCTION_5 + Function 5 + 0x5 + + + FUNCTION_6 + Function 6 + 0x6 + + + FUNCTION_7 + Function 7 + 0x7 + + + + + EPD + Enable pull-down resistor at pad. + [3:3] + + ENUM + + DISABLE_PULL_DOWN + Disable pull-down. + 0 + + + ENABLE_PULL_DOWN + Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode. + 1 + + + + + EPUN + Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset. + [4:4] + + ENUM + + ENABLE_PULL_UP + Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode. + 0 + + + DISABLE_PULL_UP + Disable pull-up. + 1 + + + + + EHS + Select Slew rate. + [5:5] + + ENUM + + SLOW_LOW_NOISE_WITH + Slow (low noise with medium speed) + 0 + + + FAST_MEDIUM_NOISE_W + Fast (medium noise with fast speed) + 1 + + + + + EZI + Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving. + [6:6] + + ENUM + + DISABLE_INPUT_BUFFER + Disable input buffer + 0 + + + ENABLE_INPUT_BUFFER + Enable input buffer + 1 + + + + + ZIF + Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz. + [7:7] + + ENUM + + ENABLE_INPUT_GLITCH + Enable input glitch filter + 0 + + + DISABLE_INPUT_GLITCH + Disable input glitch filter + 1 + + + + + RESERVED + Reserved + [31:8] + + + + + + SFSP2_0 Pin configuration register for pins P2 0x100 read-write @@ -40331,10 +40633,315 @@ - 3 - 0x4 - 3-5 - SFSP2_%s + SFSP2_1 + Pin configuration register for pins P2 + 0x104 + read-write + 0 + 0xFFFFFFFF + + + MODE + Select pin function. + [2:0] + + ENUM + + FUNCTION_0_DEFAULT + Function 0 (default) + 0x0 + + + FUNCTION_1 + Function 1 + 0x1 + + + FUNCTION_2 + Function 2 + 0x2 + + + FUNCTION_3 + Function 3 + 0x3 + + + FUNCTION_4 + Function 4 + 0x4 + + + FUNCTION_5 + Function 5 + 0x5 + + + FUNCTION_6 + Function 6 + 0x6 + + + FUNCTION_7 + Function 7 + 0x7 + + + + + EPD + Enable pull-down resistor at pad. + [3:3] + + ENUM + + DISABLE_PULL_DOWN + Disable pull-down. + 0 + + + ENABLE_PULL_DOWN + Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode. + 1 + + + + + EPUN + Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset. + [4:4] + + ENUM + + ENABLE_PULL_UP + Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode. + 0 + + + DISABLE_PULL_UP + Disable pull-up. + 1 + + + + + EHS + Select Slew rate. + [5:5] + + ENUM + + SLOW_LOW_NOISE_WITH + Slow (low noise with medium speed) + 0 + + + FAST_MEDIUM_NOISE_W + Fast (medium noise with fast speed) + 1 + + + + + EZI + Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving. + [6:6] + + ENUM + + DISABLE_INPUT_BUFFER + Disable input buffer + 0 + + + ENABLE_INPUT_BUFFER + Enable input buffer + 1 + + + + + ZIF + Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz. + [7:7] + + ENUM + + ENABLE_INPUT_GLITCH + Enable input glitch filter + 0 + + + DISABLE_INPUT_GLITCH + Disable input glitch filter + 1 + + + + + RESERVED + Reserved + [31:8] + + + + + + SFSP2_2 + Pin configuration register for pins P2 + 0x108 + read-write + 0 + 0xFFFFFFFF + + + MODE + Select pin function. + [2:0] + + ENUM + + FUNCTION_0_DEFAULT + Function 0 (default) + 0x0 + + + FUNCTION_1 + Function 1 + 0x1 + + + FUNCTION_2 + Function 2 + 0x2 + + + FUNCTION_3 + Function 3 + 0x3 + + + FUNCTION_4 + Function 4 + 0x4 + + + FUNCTION_5 + Function 5 + 0x5 + + + FUNCTION_6 + Function 6 + 0x6 + + + FUNCTION_7 + Function 7 + 0x7 + + + + + EPD + Enable pull-down resistor at pad. + [3:3] + + ENUM + + DISABLE_PULL_DOWN + Disable pull-down. + 0 + + + ENABLE_PULL_DOWN + Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode. + 1 + + + + + EPUN + Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset. + [4:4] + + ENUM + + ENABLE_PULL_UP + Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode. + 0 + + + DISABLE_PULL_UP + Disable pull-up. + 1 + + + + + EHS + Select Slew rate. + [5:5] + + ENUM + + SLOW_LOW_NOISE_WITH + Slow (low noise with medium speed) + 0 + + + FAST_MEDIUM_NOISE_W + Fast (medium noise with fast speed) + 1 + + + + + EZI + Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving. + [6:6] + + ENUM + + DISABLE_INPUT_BUFFER + Disable input buffer + 0 + + + ENABLE_INPUT_BUFFER + Enable input buffer + 1 + + + + + ZIF + Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz. + [7:7] + + ENUM + + ENABLE_INPUT_GLITCH + Enable input glitch filter + 0 + + + DISABLE_INPUT_GLITCH + Disable input glitch filter + 1 + + + + + RESERVED + Reserved + [31:8] + + + + + + SFSP2_3 Pin configuration register for pins P2 0x10C read-write @@ -40504,6 +41111,346 @@ + SFSP2_4 + Pin configuration register for pins P2 + 0x110 + read-write + 0 + 0xFFFFFFFF + + + MODE + Select pin function. + [2:0] + + ENUM + + FUNCTION_0_DEFAULT + Function 0 (default) + 0x0 + + + FUNCTION_1 + Function 1 + 0x1 + + + FUNCTION_2 + Function 2 + 0x2 + + + FUNCTION_3 + Function 3 + 0x3 + + + FUNCTION_4 + Function 4 + 0x4 + + + FUNCTION_5 + Function 5 + 0x5 + + + FUNCTION_6 + Function 6 + 0x6 + + + FUNCTION_7 + Function 7 + 0x7 + + + + + EPD + Enable pull-down resistor at pad. + [3:3] + + ENUM + + DISABLE_PULL_DOWN + Disable pull-down. + 0 + + + ENABLE_PULL_DOWN + Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode. + 1 + + + + + EPUN + Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset. + [4:4] + + ENUM + + ENABLE_PULL_UP + Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode. + 0 + + + DISABLE_PULL_UP + Disable pull-up + 1 + + + + + RESERVED + Reserved + [5:5] + + + + EZI + Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad. + [6:6] + + ENUM + + DISABLE_INPUT_BUFFER + Disable input buffer + 0 + + + ENABLE_INPUT_BUFFER + Enable input buffer + 1 + + + + + ZIF + Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz. + [7:7] + + ENUM + + ENABLE_INPUT_GLITCH + Enable input glitch filter + 0 + + + DISABLE_INPUT_GLITCH + Disable input glitch filter + 1 + + + + + EHD + Select drive strength. + [9:8] + + ENUM + + NORMAL_DRIVE_4_MA_D + Normal-drive: 4 mA drive strength + 0x0 + + + MEDIUM_DRIVE_8_MA_D + Medium-drive: 8 mA drive strength + 0x1 + + + HIGH_DRIVE_14_MA_DR + High-drive: 14 mA drive strength + 0x2 + + + ULTRA_HIGH_DRIVE_20 + Ultra high-drive: 20 mA drive strength + 0x3 + + + + + RESERVED + Reserved + [31:10] + + + + + + SFSP2_5 + Pin configuration register for pins P2 + 0x114 + read-write + 0 + 0xFFFFFFFF + + + MODE + Select pin function. + [2:0] + + ENUM + + FUNCTION_0_DEFAULT + Function 0 (default) + 0x0 + + + FUNCTION_1 + Function 1 + 0x1 + + + FUNCTION_2 + Function 2 + 0x2 + + + FUNCTION_3 + Function 3 + 0x3 + + + FUNCTION_4 + Function 4 + 0x4 + + + FUNCTION_5 + Function 5 + 0x5 + + + FUNCTION_6 + Function 6 + 0x6 + + + FUNCTION_7 + Function 7 + 0x7 + + + + + EPD + Enable pull-down resistor at pad. + [3:3] + + ENUM + + DISABLE_PULL_DOWN + Disable pull-down. + 0 + + + ENABLE_PULL_DOWN + Enable pull-down. Enable both pull-down resistor and pull-up resistor for repeater mode. + 1 + + + + + EPUN + Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset. + [4:4] + + ENUM + + ENABLE_PULL_UP + Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode. + 0 + + + DISABLE_PULL_UP + Disable pull-up + 1 + + + + + RESERVED + Reserved + [5:5] + + + + EZI + Input buffer enable. The input buffer is disabled by default at reset but must be enabled to transfer data from the I/O buffer to the pad. + [6:6] + + ENUM + + DISABLE_INPUT_BUFFER + Disable input buffer + 0 + + + ENABLE_INPUT_BUFFER + Enable input buffer + 1 + + + + + ZIF + Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz. + [7:7] + + ENUM + + ENABLE_INPUT_GLITCH + Enable input glitch filter + 0 + + + DISABLE_INPUT_GLITCH + Disable input glitch filter + 1 + + + + + EHD + Select drive strength. + [9:8] + + ENUM + + NORMAL_DRIVE_4_MA_D + Normal-drive: 4 mA drive strength + 0x0 + + + MEDIUM_DRIVE_8_MA_D + Medium-drive: 8 mA drive strength + 0x1 + + + HIGH_DRIVE_14_MA_DR + High-drive: 14 mA drive strength + 0x2 + + + ULTRA_HIGH_DRIVE_20 + Ultra high-drive: 20 mA drive strength + 0x3 + + + + + RESERVED + Reserved + [31:10] + + + + + 7 0x4 6-12 @@ -40661,10 +41608,7 @@ - 3 - 0x4 - 0-2 - SFSP3_%s + SFSP3_0 Pin configuration register for pins P3 0x180 read-write @@ -40818,6 +41762,314 @@ + SFSP3_1 + Pin configuration register for pins P3 + 0x184 + read-write + 0 + 0xFFFFFFFF + + + MODE + Select pin function. + [2:0] + + ENUM + + FUNCTION_0_DEFAULT + Function 0 (default) + 0x0 + + + FUNCTION_1 + Function 1 + 0x1 + + + FUNCTION_2 + Function 2 + 0x2 + + + FUNCTION_3 + Function 3 + 0x3 + + + FUNCTION_4 + Function 4 + 0x4 + + + FUNCTION_5 + Function 5 + 0x5 + + + FUNCTION_6 + Function 6 + 0x6 + + + FUNCTION_7 + Function 7 + 0x7 + + + + + EPD + Enable pull-down resistor at pad. + [3:3] + + ENUM + + DISABLE_PULL_DOWN + Disable pull-down. + 0 + + + ENABLE_PULL_DOWN + Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode. + 1 + + + + + EPUN + Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset. + [4:4] + + ENUM + + ENABLE_PULL_UP + Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode. + 0 + + + DISABLE_PULL_UP + Disable pull-up. + 1 + + + + + EHS + Select Slew rate. + [5:5] + + ENUM + + SLOW_LOW_NOISE_WITH + Slow (low noise with medium speed) + 0 + + + FAST_MEDIUM_NOISE_W + Fast (medium noise with fast speed) + 1 + + + + + EZI + Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving. + [6:6] + + ENUM + + DISABLE_INPUT_BUFFER + Disable input buffer + 0 + + + ENABLE_INPUT_BUFFER + Enable input buffer + 1 + + + + + ZIF + Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz. + [7:7] + + ENUM + + ENABLE_INPUT_GLITCH + Enable input glitch filter + 0 + + + DISABLE_INPUT_GLITCH + Disable input glitch filter + 1 + + + + + RESERVED + Reserved + [31:8] + + + + + + SFSP3_2 + Pin configuration register for pins P3 + 0x188 + read-write + 0 + 0xFFFFFFFF + + + MODE + Select pin function. + [2:0] + + ENUM + + FUNCTION_0_DEFAULT + Function 0 (default) + 0x0 + + + FUNCTION_1 + Function 1 + 0x1 + + + FUNCTION_2 + Function 2 + 0x2 + + + FUNCTION_3 + Function 3 + 0x3 + + + FUNCTION_4 + Function 4 + 0x4 + + + FUNCTION_5 + Function 5 + 0x5 + + + FUNCTION_6 + Function 6 + 0x6 + + + FUNCTION_7 + Function 7 + 0x7 + + + + + EPD + Enable pull-down resistor at pad. + [3:3] + + ENUM + + DISABLE_PULL_DOWN + Disable pull-down. + 0 + + + ENABLE_PULL_DOWN + Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode. + 1 + + + + + EPUN + Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset. + [4:4] + + ENUM + + ENABLE_PULL_UP + Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode. + 0 + + + DISABLE_PULL_UP + Disable pull-up. + 1 + + + + + EHS + Select Slew rate. + [5:5] + + ENUM + + SLOW_LOW_NOISE_WITH + Slow (low noise with medium speed) + 0 + + + FAST_MEDIUM_NOISE_W + Fast (medium noise with fast speed) + 1 + + + + + EZI + Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving. + [6:6] + + ENUM + + DISABLE_INPUT_BUFFER + Disable input buffer + 0 + + + ENABLE_INPUT_BUFFER + Enable input buffer + 1 + + + + + ZIF + Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz. + [7:7] + + ENUM + + ENABLE_INPUT_GLITCH + Enable input glitch filter + 0 + + + DISABLE_INPUT_GLITCH + Disable input glitch filter + 1 + + + + + RESERVED + Reserved + [31:8] + + + + + SFSP3_3 Pin configuration register for pins P3 @@ -41761,10 +43013,7 @@ - 3 - 0x4 - 0-2 - SFSP8_%s + SFSP8_0 Pin configuration register for pins P8 0x400 read-write @@ -41856,19 +43105,176 @@ - EHS - Select Slew rate. + RESERVED + Reserved [5:5] + + + EZI + Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving. + [6:6] ENUM - SLOW_LOW_NOISE_WITH - Slow (low noise with medium speed) + DISABLE_INPUT_BUFFER + Disable input buffer 0 - FAST_MEDIUM_NOISE_W - Fast (medium noise with fast speed) + ENABLE_INPUT_BUFFER + Enable input buffer + 1 + + + + + ZIF + Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz. + [7:7] + + ENUM + + ENABLE_INPUT_GLITCH + Enable input glitch filter + 0 + + + DISABLE_INPUT_GLITCH + Disable input glitch filter + 1 + + + + + RESERVED + Reserved + [7:7] + + + + EHD + Select drive strength + [9:8] + + ENUM + + STANDARD_DRIVE_4_MA + Standard drive: 4 mA drive strength + 0x0 + + + MEDIUM_DRIVE_8_MA_D + Medium drive: 8 mA drive strength + 0x1 + + + HIGH_DRIVE_14_MA_DR + High drive: 14 mA drive strength + 0x2 + + + ULTRA_HIGH_DRIVE_20 + Ultra-high drive: 20 mA drive strength + 0x3 + + + + + RESERVED + Reserved + [31:10] + + + + + + SFSP8_1 + Pin configuration register for pins P8 + 0x404 + read-write + 0 + 0xFFFFFFFF + + + MODE + Select pin function. + [2:0] + + ENUM + + FUNCTION_0_DEFAULT + Function 0 (default) + 0x0 + + + FUNCTION_1 + Function 1 + 0x1 + + + FUNCTION_2 + Function 2 + 0x2 + + + FUNCTION_3 + Function 3 + 0x3 + + + FUNCTION_4 + Function 4 + 0x4 + + + FUNCTION_5 + Function 5 + 0x5 + + + FUNCTION_6 + Function 6 + 0x6 + + + FUNCTION_7 + Function 7 + 0x7 + + + + + EPD + Enable pull-down resistor at pad. + [3:3] + + ENUM + + DISABLE_PULL_DOWN + Disable pull-down. + 0 + + + ENABLE_PULL_DOWN + Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode. + 1 + + + + + EPUN + Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset. + [4:4] + + ENUM + + ENABLE_PULL_UP + Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode. + 0 + + + DISABLE_PULL_UP + Disable pull-up. 1 @@ -41909,12 +43315,216 @@ - - RESERVED - Reserved - [31:8] + + RESERVED + Reserved + [7:7] + + + EHD + Select drive strength + [9:8] + + ENUM + + STANDARD_DRIVE_4_MA + Standard drive: 4 mA drive strength + 0x0 + + + MEDIUM_DRIVE_8_MA_D + Medium drive: 8 mA drive strength + 0x1 + + + HIGH_DRIVE_14_MA_DR + High drive: 14 mA drive strength + 0x2 + + + ULTRA_HIGH_DRIVE_20 + Ultra-high drive: 20 mA drive strength + 0x3 + + + + + RESERVED + Reserved + [31:10] + + + + + + SFSP8_2 + Pin configuration register for pins P8 + 0x408 + read-write + 0 + 0xFFFFFFFF + + + MODE + Select pin function. + [2:0] + + ENUM + + FUNCTION_0_DEFAULT + Function 0 (default) + 0x0 + + + FUNCTION_1 + Function 1 + 0x1 + + + FUNCTION_2 + Function 2 + 0x2 + + + FUNCTION_3 + Function 3 + 0x3 + + + FUNCTION_4 + Function 4 + 0x4 + + + FUNCTION_5 + Function 5 + 0x5 + + + FUNCTION_6 + Function 6 + 0x6 + + + FUNCTION_7 + Function 7 + 0x7 + + + + EPD + Enable pull-down resistor at pad. + [3:3] + + ENUM + + DISABLE_PULL_DOWN + Disable pull-down. + 0 + + + ENABLE_PULL_DOWN + Enable pull-down.Enable both pull-down resistor and pull-up resistor for repeater mode. + 1 + + + + + EPUN + Disable pull-up resistor at pad. By default, the pull-up resistor is enabled at reset. + [4:4] + + ENUM + + ENABLE_PULL_UP + Enable pull-up. Enable both pull-down resistor and pull-up resistor for repeater mode. + 0 + + + DISABLE_PULL_UP + Disable pull-up. + 1 + + + + + EZI + Input buffer enable. The input buffer is disabled by default at reset and must be enabled for receiving. + [6:6] + + ENUM + + DISABLE_INPUT_BUFFER + Disable input buffer + 0 + + + ENABLE_INPUT_BUFFER + Enable input buffer + 1 + + + + + ZIF + Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz. + [7:7] + + ENUM + + ENABLE_INPUT_GLITCH + Enable input glitch filter + 0 + + + DISABLE_INPUT_GLITCH + Disable input glitch filter + 1 + + + + + RESERVED + Reserved + [7:7] + + + + EHD + Select drive strength + [9:8] + + ENUM + + STANDARD_DRIVE_4_MA + Standard drive: 4 mA drive strength + 0x0 + + + MEDIUM_DRIVE_8_MA_D + Medium drive: 8 mA drive strength + 0x1 + + + HIGH_DRIVE_14_MA_DR + High drive: 14 mA drive strength + 0x2 + + + ULTRA_HIGH_DRIVE_20 + Ultra-high drive: 20 mA drive strength + 0x3 + + + + + RESERVED + Reserved + [31:10] + + @@ -50403,12 +52013,12 @@ ENUM - THE_MESSAGE_DIRECTIO + ACCEPTANCE_FILTER The message direction bit (DIR) is used for acceptance filtering. 1 - THE_MESSAGE_DIRECTIO + NO_EFFECT The message direction bit (DIR) has no effect on acceptance filtering. 0 @@ -50421,12 +52031,12 @@ ENUM - THE_EXTENDED_IDENTIF + ACCEPTANCE_FILTER The extended identifier bit (IDE) is used for acceptance filtering. 1 - THE_EXTENDED_IDENTIF + NO_EFFECT The extended identifier bit (IDE) has no effect on acceptance filtering. 0 @@ -50523,12 +52133,12 @@ ENUM - THE_MESSAGE_OBJECT_I + THE_MESSAGE_OBJECT_IS_CONFIGURED The message object is configured and should be considered by the message handler. 1 - THE_MESSAGE_OBJECT_I + THE_MESSAGE_OBJECT_IS_IGNORED The message object is ignored by the message handler. 0 @@ -52213,12 +53823,12 @@ ENUM - DISABLE__SYNCHRONIZ + DISABLE_SYNCHRONIZATION Disable synchronization. 0 - ENABLE__SYNCHRONIZA + ENABLE_SYNCHRONIZATION Enable synchronization. 1 @@ -52324,12 +53934,12 @@ ENUM - DISABLE__SYNCHRONIZ + DISABLE_SYNCHRONIZATION Disable synchronization. 0 - ENABLE__SYNCHRONIZA + ENABLE_SYNCHRONIZATION Enable synchronization. 1 @@ -52435,12 +54045,12 @@ ENUM - DISABLE__SYNCHRONIZ + DISABLE_SYNCHRONIZATION Disable synchronization. 0 - ENABLE__SYNCHRONIZA + ENABLE_SYNCHRONIZATION Enable synchronization. 1 @@ -52546,12 +54156,12 @@ ENUM - DISABLE__SYNCHRONIZ + DISABLE_SYNCHRONIZATION Disable synchronization. 0 - ENABLE__SYNCHRONIZA + ENABLE_SYNCHRONIZATION Enable synchronization. 1 @@ -52657,12 +54267,12 @@ ENUM - DISABLE__SYNCHRONIZ + DISABLE_SYNCHRONIZATION Disable synchronization. 0 - ENABLE__SYNCHRONIZA + ENABLE_SYNCHRONIZATION Enable synchronization. 1 @@ -52768,12 +54378,12 @@ ENUM - DISABLE__SYNCHRONIZ + DISABLE_SYNCHRONIZATION Disable synchronization. 0 - ENABLE__SYNCHRONIZA + ENABLE_SYNCHRONIZATION Enable synchronization. 1 @@ -52879,12 +54489,12 @@ ENUM - DISABLE__SYNCHRONIZ + DISABLE_SYNCHRONIZATION Disable synchronization. 0 - ENABLE__SYNCHRONIZA + ENABLE_SYNCHRONIZATION Enable synchronization. 1 @@ -52990,12 +54600,12 @@ ENUM - DISABLE__SYNCHRONIZ + DISABLE_SYNCHRONIZATION Disable synchronization. 0 - ENABLE__SYNCHRONIZA + ENABLE_SYNCHRONIZATION Enable synchronization. 1 @@ -53101,12 +54711,12 @@ ENUM - DISABLE__SYNCHRONIZ + DISABLE_SYNCHRONIZATION Disable synchronization. 0 - ENABLE__SYNCHRONIZA + ENABLE_SYNCHRONIZATION Enable synchronization. 1 @@ -53212,12 +54822,12 @@ ENUM - DISABLE__SYNCHRONIZ + DISABLE_SYNCHRONIZATION Disable synchronization. 0 - ENABLE__SYNCHRONIZA + ENABLE_SYNCHRONIZATION Enable synchronization. 1 @@ -53328,12 +54938,12 @@ ENUM - DISABLE__SYNCHRONIZ + DISABLE_SYNCHRONIZATION Disable synchronization. 0 - ENABLE__SYNCHRONIZA + ENABLE_SYNCHRONIZATION Enable synchronization. 1 @@ -53444,12 +55054,12 @@ ENUM - DISABLE__SYNCHRONIZ + DISABLE_SYNCHRONIZATION Disable synchronization. 0 - ENABLE__SYNCHRONIZA + ENABLE_SYNCHRONIZATION Enable synchronization. 1 @@ -53555,12 +55165,12 @@ ENUM - DISABLE__SYNCHRONIZ + DISABLE_SYNCHRONIZATION Disable synchronization. 0 - ENABLE__SYNCHRONIZA + ENABLE_SYNCHRONIZATION Enable synchronization. 1 @@ -53666,12 +55276,12 @@ ENUM - DISABLE__SYNCHRONIZ + DISABLE_SYNCHRONIZATION Disable synchronization. 0 - ENABLE__SYNCHRONIZA + ENABLE_SYNCHRONIZATION Enable synchronization. 1 @@ -53712,8 +55322,8 @@ 0x1 - TBD__I2S0_TX_MWS - TBD - I2S0_TX_MWS + I2S0_TX_MWS + I2S0_TX_MWS 0x2 @@ -53782,12 +55392,12 @@ ENUM - DISABLE__SYNCHRONIZ + DISABLE_SYNCHRONIZATION Disable synchronization. 0 - ENABLE__SYNCHRONIZA + ENABLE_SYNCHRONIZATION Enable synchronization. 1 @@ -53898,12 +55508,12 @@ ENUM - DISABLE__SYNCHRONIZ + DISABLE_SYNCHRONIZATION Disable synchronization. 0 - ENABLE__SYNCHRONIZA + ENABLE_SYNCHRONIZATION Enable synchronization. 1 @@ -54014,12 +55624,12 @@ ENUM - DISABLE__SYNCHRONIZ + DISABLE_SYNCHRONIZATION Disable synchronization. 0 - ENABLE__SYNCHRONIZA + ENABLE_SYNCHRONIZATION Enable synchronization. 1 @@ -54125,12 +55735,12 @@ ENUM - DISABLE__SYNCHRONIZ + DISABLE_SYNCHRONIZATION Disable synchronization. 0 - ENABLE__SYNCHRONIZA + ENABLE_SYNCHRONIZATION Enable synchronization. 1 @@ -54236,12 +55846,12 @@ ENUM - DISABLE__SYNCHRONIZ + DISABLE_SYNCHRONIZATION Disable synchronization. 0 - ENABLE__SYNCHRONIZA + ENABLE_SYNCHRONIZATION Enable synchronization. 1 @@ -54347,12 +55957,12 @@ ENUM - DISABLE__SYNCHRONIZ + DISABLE_SYNCHRONIZATION Disable synchronization. 0 - ENABLE__SYNCHRONIZA + ENABLE_SYNCHRONIZATION Enable synchronization. 1 @@ -54463,12 +56073,12 @@ ENUM - DISABLE__SYNCHRONIZ + DISABLE_SYNCHRONIZATION Disable synchronization. 0 - ENABLE__SYNCHRONIZA + ENABLE_SYNCHRONIZATION Enable synchronization. 1 @@ -54579,12 +56189,12 @@ ENUM - DISABLE__SYNCHRONIZ + DISABLE_SYNCHRONIZATION Disable synchronization. 0 - ENABLE__SYNCHRONIZA + ENABLE_SYNCHRONIZATION Enable synchronization. 1 @@ -54690,12 +56300,12 @@ ENUM - DISABLE__SYNCHRONIZ + DISABLE_SYNCHRONIZATION Disable synchronization. 0 - ENABLE__SYNCHRONIZA + ENABLE_SYNCHRONIZATION Enable synchronization. 1 @@ -54806,12 +56416,12 @@ ENUM - DISABLE__SYNCHRONIZ + DISABLE_SYNCHRONIZATION Disable synchronization. 0 - ENABLE__SYNCHRONIZA + ENABLE_SYNCHRONIZATION Enable synchronization. 1 @@ -54922,12 +56532,12 @@ ENUM - DISABLE__SYNCHRONIZ + DISABLE_SYNCHRONIZATION Disable synchronization. 0 - ENABLE__SYNCHRONIZA + ENABLE_SYNCHRONIZATION Enable synchronization. 1 @@ -55068,12 +56678,12 @@ ENUM - DISABLE__SYNCHRONIZ + DISABLE_SYNCHRONIZATION Disable synchronization. 0 - ENABLE__SYNCHRONIZA + ENABLE_SYNCHRONIZATION Enable synchronization. 1 @@ -55186,12 +56796,12 @@ ENUM - DISABLE__SYNCHRONIZ + DISABLE_SYNCHRONIZATION Disable synchronization. 0 - ENABLE__SYNCHRONIZA + ENABLE_SYNCHRONIZATION Enable synchronization. 1 @@ -55308,12 +56918,12 @@ ENUM - DISABLE__SYNCHRONIZ + DISABLE_SYNCHRONIZATION Disable synchronization. 0 - ENABLE__SYNCHRONIZA + ENABLE_SYNCHRONIZATION Enable synchronization. 1 @@ -55425,12 +57035,12 @@ ENUM - DISABLE__SYNCHRONIZ + DISABLE_SYNCHRONIZATION Disable synchronization. 0 - ENABLE__SYNCHRONIZA + ENABLE_SYNCHRONIZATION Enable synchronization. 1 @@ -55542,12 +57152,12 @@ ENUM - DISABLE__SYNCHRONIZ + DISABLE_SYNCHRONIZATION Disable synchronization. 0 - ENABLE__SYNCHRONIZA + ENABLE_SYNCHRONIZATION Enable synchronization. 1 @@ -56327,7 +57937,7 @@ 0xFFFFFFFF - TRIGGER__MASK + TRIGGER_MASK 00 = triggers off 01 = software trigger only 10 = external trigger only 11 = both triggers allowed [1:0]