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@alvadorn
Last active August 29, 2015 14:21
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library IEEE;
use IEEE.STD_LOGIC_1164.all;
ENTITY somador4_tb IS
END somador4_tb;
ARCHITECTURE somador_tb OF somador4_tb IS
SIGNAL A1, A2, Y: STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL C : STD_LOGIC;
BEGIN
TEST: ENTITY work.somador4
PORT MAP(A1, A2, Y, C);
A1 <= "0000", "1111" after 40ns,
"0001" after 80ns;
A2 <= "0000", "1111" after 40ns,
"0011" after 60ns,
"1001" after 80ns;
END somador_tb;
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